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Advance Data Sheet
July 1999
B900
Baseband Signal Processor
1 Features
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For 5 V operation:
— 12.5 ns instruction cycle time (80 MIPS)
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For 3.3 V operation:
— 16.7 ns instruction cycle time (60 MIPS)
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Power-saving features:
— Low-power CMOS technology; fully static
design
— Active power: 9.5 mW/MIPS at 5.0 V;
3.3 mW/MIPS at 3.3 V
— Low-power stopclk: 175 W at 5.0 V;
— 66 W at 3.3 V
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2 Kwords internal RAM
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24 Kwords of internal ROM
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16 x 16-bit multiplication and 36-bit accumulation
in one instruction cycle
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Two 36-bit accumulators
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Instruction cache for high-speed, program-
efficient, zero-overhead looping
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One external vectored interrupt
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Two 64 Kword address spaces
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Programmable phase-locked loop
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Three 8-bit and one 4-bit I/O ports for flexible
status or control pins
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Two interrupt timers and one watchdog timer
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High- and low-frequency clock options
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Synchronous serial interface unit
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Object code upward compatible with DSP1600
Digital Signal Processor family
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Supported by software support tools for both PC
and
UNIX* platforms
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Full-speed in-circuit emulation HDS (HD-
supported)
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One dual-channel serial I/O port
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One bit manipulation unit
*
UNIX is a registered trademark of Novell, Inc. licensed
exclusively through X/Open Company Ltd.
2 Description
The B900 is a 16-bit, fixed-point baseband signal
processor based on the DSP1600 core. It is pro-
grammable to perform a wide variety of fixed-point
signal processing functions. A member of the
DSP1600 family, the B900 includes a mix of periph-
erals specifically intended to support processing-
intensive but cost-sensitive applications. In addition
to the core, the B900 consists of the following
peripheral blocks: a programmable phase-locked
loop (PLL), synchronous serial interface unit (SSI),
four I/O ports (IOPs), two timer units, a watchdog
timer, one dual-channel serial I/O interface (SIO), a
JTAG interface, 2 Kwords of RAM, and 24 Kwords of
ROM. The B900 is specifically designed as the core
processor for a low-cost, high-performance cordless
platform. The B900, along with the Lucent Technolo-
gies Microelectronics Group CSP1009 and W9009
devices, provides all of the functionality required for
a digital-cordless application. (Please refer to the
CSP1009 and W9009 data sheets for more informa-
tion.)
The B900 is available in the following packages:
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The B900 achieves high throughput without pro-
gramming restrictions or latencies due to its parallel
pipelined architecture. The processor has an arith-
metic unit capable of a 16 x 16-bit multiplication and
36-bit accumulation, or a 32-bit ALU operation in
one instruction cycle. Data is accessed from mem-
ory through two independent addressing units.
A fully static, low-power CMOS design and a low-
power standby mode support power-sensitive equip-
ment applications.