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參數(shù)資料
| 型號： | B900M24FXX12IT |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQCC44 |
| 文件頁數(shù)： | 47/100頁 |
| 文件大小： | 1547K |
| 代理商： | B900M24FXX12IT |
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50
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.2
Register Settings (continued)
cbit<a—d> and sbit<a—d> Register Fields
* Read only. Any value written to this field is ignored.
0
≤ n ≤ 7. For IOPD 0 ≤ n ≤ 3.
See Table 19, IOP Pin Multiplexing, on page 32 and Section 4.7.2, IOPA Interrupt Circuitry, on page 31.
Note: Because the cbit and sbit registers have interrelated fields, Table 38 duplicates the information in
Table 37. auc (Arithmetic Unit Control) Register
Bit
15—9
8
7
6—4
3—2
1—0
Field
Res
RAND
X = Y =
CLR
SAT
ALIGN
Bit
Field
Value
Description
15—9
Res
—
Reserved—read as zero, write as zero.
8
RAND
0
Pseudorandom number generator (PNG) reset by writing the pi
register only outside an interrupt service routine.
1
PNG never reset by writing the pi register.
7
X = Y =
0
Normal operation.
1
Transfer statements y = Y load both the x and the y registers.
All instructions that load the high half of the y register also load
the x register. This allows single-cycle squaring (p = x
y).
6—4
CLR
1XX
Clearing yl is disabled (enabled when 0).
X1X
Clearing a1l is disabled (enabled when 0).
XX1
Clearing a0l is disabled (enabled when 0).
3—2
SAT
1X
a1 saturation on overflow is disabled (enabled when 0).
X1
a0 saturation on overflow is disabled (enabled when 0).
1—0
ALIGN
00
a0, a1
← p.
01
a0, a1
← p/4.
10
a0, a1
← p x 4 (and zeros written to the two LSBs).
11
a0, a1
← p x 2 (and zeros written to the LSB).
Table 38. cbit<a—d> (IOP Control Bit) and sbit<a—d> (IOP Status Bit) Registers
cbit<a—d> Registers
sbit<a—d> Registers
Bit
15—8
7—0
Bit
15—8
7—0
Field
MODE[7:0] DATA[7:0]
Field
DIR[7:0]
VALUE[7:0]*
DIR[n]
MODE[n]
DATA[n]
Action on IOP[n]
1 (Output)
0
Clear
1 (Output)
0
1
Set
1 (Output)
1
0
No change
1 (Output)
1
Toggle
0 (Input)
x
Input
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