參數(shù)資料
型號(hào)： B900M24FXX12IT
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件頁(yè)數(shù)： 7/100頁(yè)
文件大小： 1547K
代理商： B900M24FXX12IT
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
14
Lucent Technologies Inc.
3 Pin Information (continued)
Table 6. JTAG Test Mode Interface
Table 7. PWR/GND
Pin
Description
TCK
Test Clock. Input. JTAG serial shift clock that clocks data into TDI and out of TDO and controls
the JTAG port by latching TMS into the state machine controller.
TMS
Test Mode Select. Input. JTAG mode control signal that controls the state of the JTAG
controller. TMS is sampled on the rising edge of TCK. This pin has an internal pull-up resistor
that is typically 68 k
.
TDI
Test Data Input. Input. JTAG serial input of all serial-scanned data and instructions that is
sampled on the rising edge of TCK. This pin has an internal pull-up resistor that is typically
68 k
.
TDO
Test Data Output. 3-state Output. JTAG serial output of all serial-scanned data and status bits.
TDO changes on the falling edge of TCK.
JTSEL
JTAG Select. Input. JTSEL is multiplexed with IOPB3. This pin is sampled on the rising edge of
RSTB. If sampled high, the four multiplexed JTAG pins will be active in place of IOPC[3:0]. If
sampled low, the IOPC[3:0] pins will behave as normal IOP signals.
Pin
Description
VDDA
5.0 V or 3.3 V PLL Supply. VDDA is the positive supply for the analog blocks. Separate bypass
capacitors should be connected from VDDA to VSSA.
VSSA
PLL Ground. VSSA is the ground return for the analog blocks.
VSS
Ground. The B900 has five ground pins.
VDD
5.0 V or 3.3 V Supply. VDD is the positive supply for the digital blocks. There are five power
pins.
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