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參數資料
| 型號： | B900J24FXX12IT |
| 元件分類： | 數字信號處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件頁數： | 49/100頁 |
| 文件大小： | 1547K |
| 代理商： | B900J24FXX12IT |
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52
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.2
Register Settings (continued)
Table 40. chipo Register Fields
Bit
15—12
11
10—9
8—7
6
5—4
3
2—0
Field
Reserved
LOCK
Reserved
ROSP
LOCKOSCON
WDEN
WDCLKSEL
Reserved
Bit
Field
Description
15—12
Reserved
Write with zeros; read as zeros.
11
LOCK*
* The chipo register should be initialized once immediately after reset and can be locked to prevent any further changes to its contents by
setting the LOCK bit. Once LOCK bit has been set, the chipo register cannot be modified until a reset sequence occurs.
Lock all bits in the chipo register:
0 = chipo register contents may be changed.
1 = chipo register contents may not be modified until after next reset
sequence.
10—9
Reserved
Write with zeros; read as zeros.
8—7
ROSP[1:0]
Ring oscillator speed:
00 = minimum of 32 kHz.
01 = increase default speed approximately 36%.
10 = decrease default speed approximately 28%.
11 = decrease default speed approximately 50%.
6
LOCKOSCON
Lock oscillator ON, crystal oscillator override:
0 = allows the OSCDIS bit (clkc[1]) to control oscillator.
1 = forces the oscillator to produce a clock; takes precedence over the
OSCDIS bit (clkc[1]).
5—4
WDEN[1:0]
Watchdog timer enable bits:
00 = watchdog timer disabled.
01 = time-out after 212 watchdog clock cycles.
10 = time-out after 214 watchdog clock cycles.
11 = time-out after 216 watchdog clock cycles.
3
WDCLKSEL
Watchdog clock select:
0 = select (inputclock/128) as watchdog clock source.
1 = select internal ring oscillator as watchdog clock source; also prevents
ROSCDIS (clkc[2]) from disabling ring oscillator.
2—0
Reserved
Write with zeros; read as zeros.
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