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參數(shù)資料
| 型號： | B900J24FXX12IT |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件頁數(shù)： | 39/100頁 |
| 文件大?。?/td> | 1547K |
| 代理商： | B900J24FXX12IT |
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Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
43
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.4 Conditional Mnemonics (Flags)
Please note the following:
s
Testing the state of the counter (c0 or c1) automatically increments the counter by one.
s
The pseudorandom sequence generator (PSG) may be reset by writing any value to the pi register, except
during an interrupt service routine. While in an interrupt service routine, writing to the pi register updates the
register and does not reset the PSG. If not in an interrupt service routine, writing to the pi register resets the
PSG. (The pi register is updated, but written with the contents of the PC on the next instruction.) Interrupts must
be disabled when writing to the pi register. If an interrupt is taken after the pi write, but before pi is updated with
the PC value, the ireturn instruction does not return to the correct location. However, if the RAND bit in the auc
register is set, writing the pi register never resets the PSG. A random rounding function can be implemented with
either heads or tails.
Table 28. B900 Conditional Mnemonics
Test
Meaning
Test
Meaning
pl
Result is nonnegative (sign bit is bit 35).
mi
Result is negative.
eq
Result is equal to 0.
ne
Result is not equal to 0.
gt
Result is greater than 0.
le
Result is less than or equal to 0.
lvs
Logical overflow set.*
* Result is not representable in the 36-bit accumulators (36-bit overflow).
lvc
Logical overflow clear.
mvs
Mathematical overflow set.
Bits 35:31 are not the same (32-bit overflow).
mvc
Mathematical overflow clear.
c0ge
Counter 0 greater than or equal to 0.
c0lt
Counter 0 less than 0.
c1ge
Counter 1 greater than or equal to 0.
c1lt
Counter 1 less than 0.
heads
Pseudorandom sequence bit set.
tails
Pseudorandom sequence bit clear.
true
The condition is always satisfied
in an if instruction.
false
The condition is never satisfied
in an if instruction.
npint
Not PINT (used by JTAG).
njint
Not JINT (used by JTAG).
pllon
B900 core clock is currently phase-
locked loop (CLKPLL).
plloff
B900 core clock is not currently the
phase-locked loop (CLKPLL).
slowon
B900 core clock is currently the low-
frequency clock (CLKLOW).
slowoff
B900 core clock is not currently the low-
frequency clock (CLKLOW).
stopclk STOPCLK is set but the 2X core clock
(CLKCORE2X) has not yet stopped.
evenp
Even parity (from BMU operation).
oddp
Odd parity (from BMU operation).
nmns1
Not minus 1 (result of BMU operation).
mns1
Minus 1 (result of BMU operation).
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