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| 型號： | B900J24FXX12IT |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件頁數(shù)： | 38/100頁 |
| 文件大小： | 1547K |
| 代理商： | B900J24FXX12IT |
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B900
Advance Data Sheet
Baseband Signal Processor
July 1999
42
Lucent Technologies Inc.
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.3 Control Instructions
Table 26 shows control instructions and their required numbers of instruction cycles and program-memory words.
Required instruction cycles and program-memory words vary according to whether each instruction is executed
unconditionally or conditionally. Control instructions cannot be executed from the cache.
With the exception of ireturn, the control instructions in Table 26 can be executed conditionally. For example:
if le goto 0x0345
Table 26. Control Instructions
Control Instructions
Executed Unconditionally
Executed Conditionally
Number of
Cycles
Number of
Words
Number of
Cycles
Number of
Words
goto JA*
goto pt
call JA*
call pt
return (goto pr)
* The goto JA and call JA instructions should not be placed in the last or next-to-last instruction before the
boundary of a 4 Kword page. If the goto or call is placed there, the program counter increments to the next page
and the jump is to the next page rather than the desired current page.
2
132
ireturn (goto pi)
The ireturn instruction can only be executed unconditionally.
21
—
Table 27. Replacement Table for Control Instructions
Replace
Value
Meaning
CON
mi, pl, eq, ne, gt, le, lvs, lvc, mvs,
mvc, c0ge, c0lt, c1ge, c1lt, heads,
tails, true, false, npint, njint, plloff,
pllon, slowoff, slowon, stopclk,
rfrsh, oddp, evenp, mns1, nmns1
See Table 28 for definitions of
mnemonics.
JA
12-bit value
Least significant 12 bits of
absolute address within the
same 4 Kword memory section.
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