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參數(shù)資料
| 型號： | B900J24FXX12IT |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件頁數(shù)： | 20/100頁 |
| 文件大?。?/td> | 1547K |
| 代理商： | B900J24FXX12IT |
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26
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.5
Clock Generation
There are multiple options for clock generation in the B900. The device includes a crystal oscillator to be used with
an external crystal, but can also accept a direct-driven input clock. (In real applications, the crystal oscillator clock is
always selected by default.) An internal independently enabled PLL is also provided, allowing the input clock to be
multiplied up to provide a high-frequency 2X core clock of up to 160 MHz. If the PLL is not used, then a 2X clock (2
times the MIPS rate) must be provided externally. This 2X clock, whether provided externally or generated internally
by the PLL, is internally divided by two to generate the B900 core clock. An internal low-power oscillator is also pro-
vided which can be used to clock the B900 core for power savings.
4.5.1 Functional Overview
The clock generator for the B900 incorporates a wide range of options, including a crystal oscillator, PLL, low-fre-
quency divider, and an internal ring oscillator. The clock generates the outputs shown in Table 14.
Table 14. Clock Options
Clock Option
Signal
Generated by/Output
Input Crystal/
Clock
CLKIN
Output of the oscillator. The crystal oscillator circuit provides the device input clock
and is controlled by the OSCBYP input pin.
Ring Oscillator
CLKRING
The internal ring oscillator defaults to a minimum of 32 kHz. Even though the
internal oscillator frequency is not exact, it may be measured against the crystal
oscillator output and coarsely adjusted by setting the ROSP[1:0] bits in the chipo
configuration settings in the clock generator.
Wait-stated
DSP Clock
CLKWAIT
The wait-stated clock generated by the core.
PLL Clock
CLKPLL
The PLL consists of the phase detector, loop filter, voltage-controlled oscillator
(VCO), M divider, K divider, and N divider and provides output clock frequencies
ranging from 50 MHz to 160 MHz. The value of M, K, and N are set in the pllc
register (see Table 47).
B900 2X Core
Clock
CLKCORE2X
Generated by the PLL, low-frequency clock, input clock, or ring oscillator and
output to clock the core.
Stop-Clock
—
A power-saving mode that completely turns off CLKCORE2X. Any reset (powerup,
pin, or JTAG), IOPA interrupt, INTB, TIMER1, or TIMER0 interrupt clears
STOPCLK.
Free-running
DSP Clock
CLKFREE
Generated by the core clock (the 2X core clock divided by two) and output to all the
peripherals. The timers count cycles of CLKFREE divided by a prescaler that is set
in the timerc register (see Table 53). CLKFREE is also the MIPS rate of the B900.
Watchdog
Clock
CLKWD
Generated by the input clock, divided by 128, or the ring oscillator and output to the
watchdog timer. The watchdog timer clock is selectable between CLKIN divided by
128 or CLKRING. Its time-out period is specified by bits WDEN[1:0] in the chipo
register (see Table 40).
DOUT
—
Provides digital output depending on the setting of DOUTMUX[3:0] in the clkc
register (see Table 41).
TIMER0 Clock
CLKTIM0
Multiplexer control signal: SELTIMCKO, from the timerc register (see Table 53).
TIMER1 Clock
CLKTIM1
Multiplexer control signal: SELTIMCKI, from the timerc register (see Table 53).
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