參數(shù)資料
型號(hào)： B900J24FXX12IT
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 59.88 MHz, OTHER DSP, PQFP44
文件頁數(shù)： 36/100頁
文件大?。?/td> 1547K
代理商： B900J24FXX12IT
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
40
Lucent Technologies Inc.
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.1 F1 Multiply/ALU Instructions (continued)
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the
corresponding CLR bit in the auc register is zero. auc is cleared by reset.
Table 22. F1 Multiply/ALU Instructions
F1 Function Statement
Transfer
Statement*
* The [l] is an optional argument that specifies the low 16 bits of aT or y.
Transfer Statement
Cycles
If an X space access and a Y space access are made to the same bank of DPRAM in one
instruction, add one cycle.
Not Using
Cache
Using
Cache
p = x
y
p = x
y becomes a single-cycle squaring operation if the auc bit 7 is set. With bit 7 set, a
transfer statement of the form y = Y loads the x register and the y register with the same
number, so p = x
y results in the square.
y = Y, x = X
2
1
aD = p, p = x
y
y = aT, x = X
2
1
aD = aS + p, p = x
y
y[l] = Y
1
aD = aS – p, p = x
y
aT[l] = Y
1
aD = p
x = Y
1
aD = aS + p
Y
1
aD = aS – p
Y = y[l]
2
aD = y
Y = aT[l]
2
aD = aS + y
Z:y, x = X
2
aD = aS – y
Z:y[l]
2
aD = aS & y
Z:aT[l]
2
aD = aS | y
—
1
aD = aS ^ y
—
1
aS – y
—
1
aS & y
—
1
Table 23. Replacement Table for F1 Multiply/ALU Instructions
Replace
Value
Meaning
aD, aS, aT
a0, a1
One of the DAU accumulators.
X
*pt++, *pt++i
X space memory location pointed to by pt.
pt is postmodified by +1 and i, respectively.
Y
*rM, *rM++, *rM– –, *rM++j
RAM location pointed to by rM (M = 0, 1, 2, 3).
rM is postmodified by 0, +1, –1, or j, respectively.
Z
*rMzp, *rMpz, *rMm2, *rMjk
Read/write compound addressing. rM (M = 0, 1, 2, 3) is used
twice. First, postmodified by 0, +1, –1, or j, respectively; and,
second, postmodified by +1, 0, +2, or k, respectively.
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