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參數(shù)資料
| 型號(hào)： | B900J24FXX12IT |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
| 文件頁(yè)數(shù)： | 6/100頁(yè) |
| 文件大?。?/td> | 1547K |
| 代理商： | B900J24FXX12IT |
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Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
13
3 Pin Information (continued)
Table 5. I/O Port Interface (IOP)
Pin
Description
IOPA[7:0]
I/O Port A. Bidirectional. These pins may be individually configured to be inputs or outputs. As
outputs, each bit may be set, cleared, or toggled under program control. As inputs, they may be
read. Note that IOPA is not available in the 28-pin SOJ package.
IOPB[7:0]
I/O Port B. Bidirectional. These pins may be individually configured to be inputs or outputs. As
outputs, each bit may be set, cleared, or toggled under program control. As inputs, they may be
read. Note that IOPB pins are multiplexed as follows:
s
IOPB0/INTB
s
IOPB1/OSCBYP
s
IOPB2/SLDB
s
IOPB3/JTSEL
s
IOPB4/SLDA
s
IOPB5/SCLK
s
IOPB6/SDO
s
IOPB7/SDI
IOPC[7:0]
I/O Port C. Bidirectional. These pins may be individually configured to be inputs or outputs. As
outputs, each bit may be set, cleared, or toggled under program control. As inputs, they may be
read. Note that IOPC pins are multiplexed with other pins as follows:
s
IOPC0/TMS
s
IOPC1/TCK
s
IOPC2/TDI
s
IOPC3/TDO
s
IOPC4/SSN
s
IOPC5/SCK
s
IOPC6/MDOSDI
s
IOPC7/MDISDO
IOPD[3:0]
I/O Port D. Bidirectional. These pins may be individually configured to be inputs or outputs. As
outputs, each bit may be set, cleared, or toggled under program control. As inputs, they may be
read.
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