
12
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
3 Pin Information (continued)
Table 3. System Interface
Table 4. Synchronous Serial Interface (SSI)*
* The SSI is configurable for either master mode or slave mode, selectable by the ssic register.
Pin
Description
XTALA, XTALB Crystal Oscillator. Input/Output. The external crystal is connected between these two pins,
which places the crystal in the feedback loop of the on-chip crystal oscillator. The output of the
crystal oscillator is used as a reference for the phase-locked loop (PLL). The frequency of the
oscillator input must be 4.096 MHz.
RSTB
Reset. Bidirectional (Schmitt trigger). Negative assertion. A high-to-low transition on RSTB
causes the B900 to enter the reset state. Upon deassertion, the B900 begins execution from
location 0x0000.
Note: This input contains a Schmitt trigger providing a hysteresis between positive- and nega-
tive-going transitions. When the watchdog timer times out, RSTB is pulled low.
INTB
Interrupt. Input (Schmitt trigger). Negative edge triggered. External interrupt to the B900. This
input contains a Schmitt trigger providing a hysteresis between positive- and negative-going tran-
sitions. An interrupt is posted when a negative-going transition is detected. Also, note that there
is no acknowledge pin. External hardware must guarantee that the interrupt service routine has
completed before issuing another interrupt on INTB.
Any activity on INTB is not recognized during the interrupt service routine and must be reissued
after the interrupt service routine has completed.
DOUT
Digital Output. Output. The default of the pin is to output a logic low. DOUT is selectable through
tal clock, the low-frequency clock, the free-running core clock, the wait-stated core clock, the 2X
core clock, a logic 0, or a logic 1.
OSCBYP
Oscillator Bypass Input. OSCBYP is multiplexed with IOPBI. This pin is sampled on the rising
edge of RSTB. If sampled low, the crystal oscillator circuit will be used with an external crystal. If
sampled high, the crystal oscillator circuit will be bypassed with a direct-driven clock applied to
XTALA.
Pin
Description
SCK
SSI Clock. Bidirectional. If SSI is configured in master mode, this pin is an output providing a
clock to the slave devices. If SSI is configured in slave mode, this pin is an input that takes in the
serial clock.
MDOSDI
Master Data Out/Slave Data In. Bidirectional. If SSI is configured in master mode, this pin is the
serial data output. If SSI is configured in slave mode, this pin is the serial data input. The SSI is
MDISDO
Master Data In/Slave Data Out. Bidirectional. If SSI is configured in master mode, this pin is the
serial data input. If SSI is configured in slave mode, this pin is the serial data output. The SSI is
SSN
Serial Select. Input. Negative assertion. When SSI is configured as a slave, the assertion of
SSN signals the slave that it is being addressed to transfer data with the master device. If this pin
is asserted while SSI is configured as a master, a mode fault is detected by SSI. Alternatively, in
master mode, this pin can be configured to act as a general-purpose IOP pin.