
REV. A
ADV7310/ADV7311
–9–
t9
t11
t10
t12
Cb0
Y0
Cr0
Y1
Crxxx
Yxxx
t14
t13
CLKIN_A
Y9–Y0
P_VSYNC,
P_HSYN
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
C,
P_BLANK
CONTROL
INPUTS
CONTROL
OUTPUTS
Figure 5. PS 4:2:2 1
10-Bit Interleaved at 54 MHz
HSYNC/VSYNC Input Mode [Input Mode 111]
t9
t11
t10
t12
t11
t12
t13
t14
CLKIN_B*
*CLKIN_B USED IN THIS PS ONLY MODE.
Y9–Y
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
0
CONTROL
OUTPUTS
3FF
00
XY
Cb0
Y0
Cr0
Y1
Figure 6. PS Only 4:2:2 1
10-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]
t9
t11
t10
t12
t14
t13
CLKIN_A
Y9–Y0
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
CONTROL
OUTPUTS
3FF
00
XY
Cb0
Y0
Cr0
Y1
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0
01 BIT-1
Figure 7. PS Only 4:2:2 1
10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]