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參數(shù)資料
| 型號： | ADV7311KST |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 產品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | DVD，SD/HD |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. A
–30–
ADV7310/ADV7311
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be
set to 1:
Address 0x7C, Bit 1 (Global 10-Bit Enable)
Address 0x13, Bit 2 (HD 10-Bit Enable)
Address 0x48, Bit 4 (SD 10-Bit Enable)
Note that the ADV7310 defaults to simultaneous standard
definition and progressive scan on power-up.
Address[01h] : Input Mode = 011
Standard Definition Only
Address[01h] : Input Mode = 000
The 8-/10-bit multiplexed input data is input on Pins S9–S0 (or
Y9–Y0, depending on Register Address 01h, Bit 7), with S0 being
the LSB in 10-bit input mode. Input standards supported are
ITU-R BT.601/656. In 16-bit input mode, the Y pixel data is
input on Pins S9–S2 and CrCb data on Pins C9–C2. The 27 MHz
clock input must be input on Pin CLKIN_A. Input sync signals
are optional and are input on the
S_VSYNC, S_HSYNC, and
S_BLANK pins.
MPEG2
DECODER
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0] OR Y[9:0]*
27MHz
3
10
YCrCb
ADV7310/
ADV7311
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 22. SD Only Input Mode
Progressive Scan Only or HDTV Only
Address[01h] Input Mode 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0. In
4:4:4 input mode, Y data is input on Pins Y9–Y0, Cb data on
Pins C9–C0, and Cr data on Pins S9–S0. If the YCrCb data
does not conform to SMPTE 293M (525p), ITU-R BT.1358M
(625p), SMPTE 274M[1080i], SMPTE 296M[720p], or
BTA-T1004/1362, the async timing mode must be used. RGB
data can only be input in 4:4:4 format in PS input mode only or
HDTV input mode only when HD RGB input is enabled. G data
is input on Pins Y9–Y0, R data on S9–S0, and B data on C9–C0.
The clock signal must be input on Pin CLKIN_A.
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
C[9:0]
10
Cb
S[9:0]
Y[9:0]
INTERLACED TO
PROGRESSIVE
YCrCb
10
Cr
10
Y
3
27MHz
ADV7310/
ADV7311
Figure 23. Progressive Scan Input Mode
Simultaneous Standard Definition and
Progressive Scan or HDTV
Address[01h] : Input Mode 011(SD 10-Bit, PS 20-Bit) or
101(SD and HD, SD Oversampled), 110(SD and HD, HD
Oversampled), Respectively
YCrCb, PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode the HD Y data is input on
Pins Y9–Y0 and the HD CrCb data on C9–C0. If PS 4:2:2 data
is interleaved onto a single 10-bit bus, Y9–Y0 are used for the
input port. The input data is to be input at 27 MHz, with the
data being clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accord-
ingly. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],
SMPTE 296M[720p], or BTA-T1004, the async timing mode
must be used.
The 8- or 10-bit standard definition data must be compliant
with ITU-R BT.601/656 in 4:2:2 format. Standard definition
data is input on Pins S9–S0, with S0 being the LSB. Using
8-bit input format, the data is input on Pins S9–S2. The clock
input for SD must be input on CLKIN_A and the clock input
for HD must be input on CLKIN_B. Synchronization signals are
optional. SD syncs are input on Pins
S_VSYNC, S_HSYNC,
and
S_BLANK. HD syncs on Pins P_VSYNC, P_HSYNC,
and
P_BLANK.
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
MPEG2
DECODER
3
27MHz
10
YCrCb
INTERLACED TO
PROGRESSIVE
10
CrCb
10
Y
3
27MHz
S[9:0]
C[9:0]
Y[9:0]
ADV7310/
ADV7311
Figure 24. Simultaneous PS and SD Input
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