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參數(shù)資料
| 型號： | ADV7311KST |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 產(chǎn)品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | DVD，SD/HD |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. A
–36–
ADV7310/ADV7311
SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2, 1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bit 1, 2], the ADV7310/ADV7311 can be used in
(a) timing reset mode, (b) subcarrier phase reset mode, or (c)
RTC mode.
a. A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will commence counting again,
the field count will start on Field 1, and the subcarrier phase
will be reset.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.
b. In subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to
zero on the field following the subcarrier phase reset when the
SD RTC/TR/SCR control bits at Address 44h are set to 01.
DISPLAY
NO TIMING RESET APPLIED
TIMING RESET APPLIED
START OF FIELD 4 OR 8
FSC PHASE = FIELD 4 OR 8
FSC PHASE = FIELD 1
TIMING RESET PULSE
307
310
307
1
2
3
4
5
6
7
21
313
320
DISPLAY
START OF FIELD 1
Figure 30. Timing Reset Timing Diagram
NO FSC RESET APPLIED
FSC PHASE = FIELD 4 OR 8
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
FSC RESET APPLIED
FSC RESET PULSE
FSC PHASE = FIELD 1
307
310
313
320
DISPLAY
START OF FIELD 4 OR 8
Figure 31. Subcarrier Reset Timing Diagram
This reset signal will have to be held high for a minimum of
one clock cycle.
Since the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC].
The reset of the phase will then occur on the next field, i.e.,
Field 1, being lined up correctly with the internal counters.
The field count register at Address 7Bh can be used to iden-
tify the number of the active field.
c. In RTC mode, the ADV7310/ADV7311 can be used to lock
to an external video source. The real-time control mode allows
the ADV7310/ADV7311 to automatically alter the subcarrier
frequency to compensate for line length variations. When the
part is connected to a device that outputs a digital data stream
in the RTC format, such as an ADV7183A video decoder
(see Figure 32), the part will automatically change to the
compensated subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is con-
tained in Bits 0 to 21. Each bit is two clock cycles long. 00h
should be written into all four subcarrier frequency registers
when this mode is used.
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| ADV7311KST | 制造商:Analog Devices 功能描述:Video IC |
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