![](http://datasheet.mmic.net.cn/Analog-Devices-Inc/ADV7311KST_datasheet_96354/ADV7311KST_6.png)
REV. A
–6–
ADV7310/ADV7311
TIMING SPECIFICATIONS (V
AA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET = 3040
,
RLOAD = 300
. All specifications TMIN to TMAX (0 C to 70 C), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
MPU PORT
1
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulsewidth, t1
0.6
s
SCLOCK Low Pulsewidth, t2
1.3
s
Hold Time (Start Condition), t3
0.6
s
First clock generated after this period
Setup Time (Start Condition), t4
0.6
s
relevant for repeated start condition
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
s
RESET Low Time
100
ns
ANALOG OUTPUTS
Analog Output Delay
2
7ns
Output Skew
1
ns
CLOCK CONTROL AND PIXEL PORT
3
fCLK
27
MHz
Progressive scan mode
fCLK
81
MHz
HDTV mode/async mode
Clock High Time, t9
40
% of one clk cycle
Clock Low Time, t10
40
% of one clk cycle
Data Setup Time, t11
1
2.0
ns
Data Hold Time, t12
1
2.0
ns
SD Output Access Time, t13
15
ns
SD Output Hold Time, t14
5.0
ns
HD Output Access Time, t13
14
ns
HD Output Hold Time, t14
5.0
ns
PIPELINE DELAY
4
63
clk cycles
SD [2 , 16 ]
76
clk cycles
SD component mode [16 ]
35
clk cycles
PS [1 ]
41
clk cycles
PS [8 ]
36
clk cycles
HD[2 , 1 ]
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: C[9:0]; Y[9:0], S[9:0]
Control:
P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.