參數(shù)資料
型號: ADV7311KST
廠商: Analog Devices Inc
文件頁數(shù): 66/84頁
文件大?。?/td> 0K
描述: IC VID ENC 6-12BIT DAC'S 64LQFP
產(chǎn)品變化通告: ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: DVD,SD/HD
電壓 - 電源,模擬: 2.5V
電壓 - 電源,數(shù)字: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(14x14)
包裝: 托盤
REV. A
ADV7310/ADV7311
–69–
Mode 1—Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7310/ADV7311 can generate horizontal
sync and odd/even field signals. A transition of the field input
when
HSYNC is low indicates a new frame, i.e., vertical retrace.
The blank signal is optional. When the
BLANK input is disabled,
the ADV7310/ADV7311 automatically blank all normally blank
lines as per CCIR-624. Pixel data is latched on the rising clock
edge following the timing signal transitions.
HSYNC is output
on the
S_HSYNC, BLANK on S_BLANK, and FIELD on
S_VSYNC.
622
623
624
625
1234
5
67
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
HSYNC
BLANK
FIELD
HSYNC
BLANK
Figure 83. SD Slave Mode 1 (PAL)
FIELD
PIXEL
DATA
PAL = 12
CLOCK/2
NTSC = 16
CLOCK/2
PAL = 132
CLOCK/2
NTSC = 122
CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
Figure 84. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave
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