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參數(shù)資料
| 型號： | ADV7311KST |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 產(chǎn)品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | DVD，SD/HD |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（14x14） |
| 包裝： | 托盤 |
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REV. A
ADV7310/ADV7311
–31–
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
SDTV
3
27MHz
10
YCrCb
10
CrCb
10
Y
3
74.25MHz
1080i
OR
720p
S[9:0]
C[9:0]
Y[9:0]
ADV7310/
ADV7311
HDTV
DECODER
Figure 25. Simultaneous HD and SD Input
If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
t
DELAY
9.25ns OR
t
DELAY
27.75ns
CLKIN_A
CLKIN_B
Figure 26. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-/10-bit bus and is
input on Pins Y9–Y0. When a 27 MHz clock is supplied, the data
is clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.
The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.
3FF
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y9–Y0
Cb0
Figure 27a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
3FF
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y9–Y0
Y0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 27b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
PIXEL INPUT
DATA
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Figure 27c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
MPEG2
DECODER
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
Y[9:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
10
3
27MHz OR 54MHz
YCrCb
ADV7310/
ADV7311
Figure 28. 1
10-Bit PS at 27 MHz or 54 MHz
Table I provides an overview of all possible input configurations.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADV7311KST | 制造商:Analog Devices 功能描述:Video IC |
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