參數(shù)資料
型號： ADV7162KS220
廠商： ANALOG DEVICES INC
元件分類： 顯示控制器
英文描述： 96-Bit, 220 MHz True-Color Video RAM-DAC
中文描述： 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封裝： PLASTIC, QFP-160
文件頁數(shù)： 43/44頁
文件大?。?/td> 668K
代理商： ADV7162KS220
ADV7160/ADV7162
REV. 0
–43–
PAGE INDEX
Topic
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 1 & 15
ADV7160/ADV7162 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
ADV7160/ADV7162 SPECIFICATIONS . . . . . . . . . . . . . . . . . 2
ADV7160/ADV7162 TIMING CHARACTERISTICS . . . . . 3-5
TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . 11
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . 13-14
CIRCUIT DETAILS AND OPERATION . . . . . . . . . . . . . . . . 15
PIXEL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
CLOCK CONTROL CIRCUIT . . . . . . . . . . . . . . . . . . . . . 16-17
CLOCK CONTROL SIGNALS . . . . . . . . . . . . . . . . . . . . . 17-18
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
COLOR VIDEO MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PIXEL PORT MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . 19-21
MULTIPLEXING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22
MPU PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
INTERNAL REGISTER CONFIGURATION . . . . . . . . . . . . 23
COLOR PALETTE ACCESS . . . . . . . . . . . . . . . . . . . . . . 24-25
ON-CHIP REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pixel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29
Command Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30
Command Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL R Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PLL V Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CURSOR DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 31-32
Cursor X-Low and X-High Register . . . . . . . . . . . . . . . . . . . 31
Cursor Y-Low & Y-High Register . . . . . . . . . . . . . . . . . . . . . 31
Cursor Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Y Coordinate Even . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Y Coordinate Odd . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Cursor Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 31–32
DACS & VIDEO OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . 32-33
APPENDIX 1
Board Design and Layout Considerations . . . . . . . . . . . . 34-35
APPENDIX 2
Typical Frame Buffer Interface . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX 3
10-Bit DACs and Gamma Correction . . . . . . . . . . . . . . . . . . 37
APPENDIX 4
Initialization and Programming . . . . . . . . . . . . . . . . . . . . 38-39
APPENDIX 5
Signature Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
APPENDIX 6
JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
APPENDIX 7
Thermal and Environmental Considerations . . . . . . . . . . . . . 42
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Page
FIGURE INDEX
Figure
1
2
3
4
5
Title
Load Circuit for Data-Bus Access &Relinquish Times
JTAG Port Timing
LOADOUT vs. Pixel Clock Input
LOADIN vs. Pixel Input Data
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (8:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (8:1 Mode)
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (4:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (4:1 Mode)
Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (2:1 Mode)
Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (2:1 Mode)
Pixel Clock Input vs. Programmable Clock Output
SCKIN vs. SCKOUT
Analog Output Response vs, Pixel Clock
MPU Timing
Multiplexed Color Inputs
Clock Control Circuit
LOADOUT vs. Pixel Clock
SCKOUT Generation Circuit
Interface Using SCKIN and SCKOUT
PLL Block Diagram
PLL Transfer Function
PLL Jitter
24-Bit to 30-Bit True Color Configuration
15-Bit to 24-Bit True Color Configuration
8-Bit to 30-Bit Pseudo Color Configuration
16-Bit Tue Color Mapping Using R7–R0 and G7–G0
15-Bit True Color Mapping Using R7–R3, G7–G3 and
B7–B3
15-Bit True Color Mapping Using R6–R0 and G7–G0
16-Bit True Color (Bypass) Using R7–R0 and G7–G0
15-Bit True Color (Bypass) Using R6–R0 and G7–G0
Direct Interfacing of Video Memory
8-Bit Pseudo Color in 8:1 Multiplexing Mode
MPU Port and Register Configuration
Internal Register Configuration and Address Decoding
8-Bit Databus Using 10-Bit DACs
8-Bit Databus Using 8-Bit DACs
10-Bit Databus Using 10-Bit DACs
10-Bit Databus Using 8-Bit DACs
Mode Register 1
Command Register 1
Command Register 2
Command Register 3
Command Register 4
PLL Command Register
Cursor Control Register
DAC Output Termination
Composite Video Waveform, SYNC decoded;
Pedestal = 7.5 IRE; DAC Gain = 3996
Composite Video Waveform, SYNC decoded;
Pedestal = 0 IRE; DAC Gain = 4224
Composite Video Waveform, SYNC & TRISYNC
decoded; Pedestal = 7.5 IRE; DAC Gain = 5592
Composite Video Waveform, Pedestal = 0 IRE;
DAC Gain = 4311
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相關PDF資料
PDF描述
ADV7160KS140 96-Bit, 220 MHz True-Color Video RAM-DAC
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ADV7160KS220 96-Bit, 220 MHz True-Color Video RAM-DAC
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相關代理商/技術參數(shù)
參數(shù)描述
ADV7162KSZ140 制造商:Analog Devices 功能描述:DAC 3-CH Segment 10-bit 160-Pin MQFP
ADV7162KSZ220 制造商:Analog Devices 功能描述:DAC 3-CH Segment 10-bit 160-Pin MQFP
ADV7170 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
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ADV7170KS 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
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