參數(shù)資料
型號(hào)： ADV7162KS220
廠商： ANALOG DEVICES INC
元件分類(lèi)： 顯示控制器
英文描述： 96-Bit, 220 MHz True-Color Video RAM-DAC
中文描述： 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 29/44頁(yè)
文件大?。?/td> 668K
代理商： ADV7162KS220
ADV7160/ADV7162
REV. 0
–29–
Figure 42. Command Register 3 (CR3) (CR39–CR30)
COMMAND REGISTER 4 (CR4)
(ADDRESS REG (A10–A0) = 008H)
This register contains a number of control bits as shown in the
diagram. CR4 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR49 and CR48 are both reserved).
Figure 43 shows the various operations under the control of
CR4. This register can be read from as well written to. In read
mode, CR49 and CR48 are both returned as zeros.
COMMAND REGISTER 4-BIT DESCRIPTION
HDTV SYNC Enable (CR40)
This bit specifies whether the video
TRISYNC
Input is to be
encoded, enabling the DAC outputs to generate a Tri-Level
Sync.
SYNC
Recognition Control on Red (CR41)
This bit specifies whether the video
SYNC
Input is to be en-
coded onto the IOR analog output or ignored.
SYNC
Recognition Control on Blue (CR42)
This bit specifies whether the video
SYNC
Input is to be en-
coded onto the IOB analog output or ignored.
Gain Control (CR44–CR43)
These bits specifies the amount of gain on the DAC depending
on the standard required. See “DAC and Video Outputs” sec-
tion for more detail. For gain settings that have no pedestal, the
pedestal is automatically disabled independently of CR23.
Signature Clock Control (CR45)
This bit enables or disables the clock to the signature analyzer.
Figure 43. Command Register 4 (CR4) (CRF49–CR40)
HDTV SYNC CONTROL
SYNC RECOGNITION
CONTROL (RED)
SYNC RECOGNITION
CONTROL (BLUE)
DAC GAIN
CR44 CR43
Reserved*
CR49
CR48
CR47
CR46
CR45
CR42
CR41
CR40
SIGNATURE CLOCK
CONTROL
CR46
SIGNATURE
RESET
SIGNATURE ACQUIRE
CR47
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
CR45
CR42
CR41
CR40
0 IGNORE
1 DECODE
0 IGNORE
1 DECODE
0 DISABLE TRI-SYNC
1 ENABLE TRI-SYNC
0 ENABLE
1 DISABLE
0 DISABLE
1 ENABLE
0 DISABLE CLOCK
1 ENABLE CLOCK
0 0 3996
0 1 4224
1 0 4311
1 1 5592
CR44
CR43
CR31 CR30
0 0 CLOCK
÷
4
0 1 CLOCK
÷
8
1 0 CLOCK
÷
16
1 1 CLOCK
÷
32
PRGCKOUT FREQUENCY
CONTROL
CR39
CR38
CR35
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
CR37
CR36
CR34
CR33
CR32
CR37
CR36
EXTRA
BLANK
PIPELINE DELAY CONTROL
(ADDS TO PIXEL PIPELINE DELAY; t
PD
)
0 0 0 t
PD
0 0 1 t
PD
+ 1 x LOADOUT
0 1 0 t
PD
+ 2 x LOADOUT
.........
.........
1 1 1 t
PD
+ 7 x LOADOUT
CR34 CR33 CR32
BLANK
PIPELINE DELAY
CR35
(0)
CR37 CR36
0 0 1:1 MUXING: LOADOUT = CLOCK
÷
1
0 1 2:1 MUXING: LOADOUT = CLOCK
÷
2
1 0 8:1 MUXING: LOADOUT = CLOCK
÷
8 (PSEUDO COLOR ONLY)
1 1 4:1 MUXING: LOADOUT = CLOCK
÷
4
Pixel Multiplex Control
ZERO SHOULD
BE WRITTEN TO
THIS BIT
RESERVED*
相關(guān)PDF資料
PDF描述
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