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參數(shù)資料
| 型號： | ADV7162KS220 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 96-Bit, 220 MHz True-Color Video RAM-DAC |
| 中文描述： | 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ADV7162KS220 |
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REV. 0
–32–
ADV7160/ADV7162
Figure 45. Cursor Control Register (CCR) (CCR9–CCR0)
IOR, IOG, IOB
Z
O
= 75
(CABLE)
ZS = 75
(SOURCE TERMINATION)
Z
L
= 75
(MONITOR)
DACs
Figure 46. DAC Output Termination
(Doubly Terminated 75
Load)
Figure 47. Composite Video Waveform SYNC Decoded;
Pedestal = 7.5 IRE; DAC Gain = 3996
DIGITAL-TO-ANALOG
CONVERTER (DACS) AND
VIDEO OUTPUTS
The ADV7160/ADV7162 contains three high speed video
DACs. The DAC outputs are represented as the three primary
analog color signals IOR (red video), IOG (green video) and
IOB (blue video).
DACs and Analog Outputs
The part contains three matched 10-bit digital-to-analog con-
verters. The DACs are designed using an advanced, high speed,
segmented architecture. The bit currents corresponding to each
digital input are routed to either IOR, IOG, IOB (bit = “1”) or
GND.
The analog video outputs are high impedance current sources.
Each of the these three RGB current outputs are specified to di-
rectly drive a 37.5
load (doubly terminated 75
).
Reference Input and R
SET
An external 1.23 V voltage reference is required to set up the
analog outputs of the ADV7160/ADV7162. The reference volt-
age is connected to the V
REF
input.
A resistor R
SET
is connected between the R
SET
input of the part
and ground. For specified performance, R
SET
has a value of
280
. This corresponds to the generation of RS-343A video
levels (with
SYNC
on IOG and Pedestal = 7.5 IRE) into a dou-
bly terminated 75
load. In this example DAC Gain has a
value of 3996 and is set using CR43 and CR44 of Command
Register 4. Figure 47 illustrates the resulting video waveform
and the Video Output Truth Table illustrates the corresponding
control input stimuli. On the ADV7160/ADV7162
SYNC
can
be encoded on any of the analog signals, however in practice,
SYNC
is generally encoded on either the IOG output or on all
of the video outputs.
CCR9
CCR8
CCR7
CCR6
CCR2
CCR3
CCR0
CCR5
CCR4
CCR1
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
CCR7–CCR4
(0000)
ZERO SHOULD
BE WRITTEN TO
THESE BITS
CURSOR ENABLE
CCR2
0 DISABLE
1 ENABLE
CURSOR CONTROL
CCR3
0 NONINTERLACED
1 INTERLACED
CCR1 CCR0
CURSOR MODE
Control
0 0 RESERVED
0 1 X11 CURSOR
1 0 XGA CURSOR
1 1 RESERVED
RESERVED*
92.5 IRE
7.5 IRE
40 IRE
0.340
9.05
0.054
1.44
0.286
7.62
0
0
1.000
26.67
0.714
19.05
0
0
mA
V
mA
V
OUTPUT WITHOUT
SYNC
ENCODED
OUTPUT WITH
SYNC
ENCODED
WHITE
LEVEL
BLACK
BLANK
SYNC
GREYSCALE
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PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADV7162KSZ140 | 制造商:Analog Devices 功能描述:DAC 3-CH Segment 10-bit 160-Pin MQFP |
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| ADV7170 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
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| ADV7170KS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
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