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參數(shù)資料
| 型號： | ADV7162KS220 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | 96-Bit, 220 MHz True-Color Video RAM-DAC |
| 中文描述： | 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 30/44頁 |
| 文件大?。?/td> | 668K |
| 代理商： | ADV7162KS220 |
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REV. 0
–30–
ADV7160/ADV7162
Signature Reset Control (CR46)
Taking CR46 low then high resets the signature analyzer. This is
done to give a known starting point before acquiring a signature.
Signature Acquire Control (CR47)
This bit should be set to Logic “1” for normal operation. See
“Test Diagnostic” section for more information.
COMMAND REGISTER 5 (CR5)
(Address Reg (A10–A0) = 00DH)
This register contains one control bit CR56. CR5 is a 10-bit
wide register. However for programming purposes, it may be
considered as an 8-bit wide register (CR59 and CR58 are both
reserved).
This register can be read from as well written to. Control Bit
CR56 selects either external clock or internal PLL operation. If
the internal PLL is to be used, Logic “1” should be written to
CR56.This should be set up immediately after power up. In
write mode, zero should be written to CR57 and CR55–CR50.
In read mode, CR59 and CR58 are both returned as zeros.
PLL COMMAND REGISTER (PCR)
(Address Reg (A10–A0) = 009H)
This register contains a number of control bits as shown in the
diagram. PCR is a 10-bit wide register. However, for program-
ming purposes, it may be considered as an 8-bit wide register
(PCR9 and PCR8 are both reserved).
Figure 44 shows the various operations under the control of
PCR. This register can be read from as well written to. In write
mode zero should be written to PCR3. In read mode PCR9 and
PCR8 are returned as zeros.
PLL Control (PCR0)
This bit enables or disables PLL.
RSEL Bit Control (PCR1)
This bit enables or disables RSEL, which together with the con-
tents of the PLL R Register affect the reference divider value of
the PLL. Reference Divider = (1 + RSEL)
×
(R+2).
VSEL Bit Control (PCR2)
This bit enables or disables VSEL, which together with the
contents of the PLL V Register and the PLL S value affect the
feedback divider value of the PLL.
Feedback Divider = (1 +
VSEL
)
×
(4(V + 2)+S).
Output Divide Control (PCR5–PCR4)
These bits control the PLL output divider. This post-scaler
is used in the generation of lower frequencies.
PLL S Control (PCR7–PCR6)
These bits set up the S value in the PLL transfer function.
This extra value provides extra control in setting the feed-
back divider value of the PLL.
Status Register
(Address Reg (A10–A0) = 00AH)
This register is a read only 10-bit register. However SR9–
SR8 are reserved bits, containing zeros and SR7–SR1 are
undefined bits and should be masked in software on read
back. Therefore, SR0 is the only relevant Bit in the Status
Register and contains a Logic “1” if one, or more of the
IOR, IOG, and IOB outputs exceed the internal voltage of
the
SENSE
comparator circuit . It can be used to deter-
mine the presence of a CRT monitor. With some diagnos-
tic code, the presence of loading on the individual RGB
lines can be determined. The reference is generated by a
voltage divider from the external voltage reference on the
V
RE
F
pin. For the proper operation, the following levels
should be applied to the comparator by the IOR, IOG and
IOB outputs:
DAC Low Voltage
≤
250 mV
DAC High Voltage
≥
450 mV
Revision Register
(Address Reg (A10–A0) = 01BH)
This register is a read only register containing the revision
of silicon.
PLL R Register
(Address Reg (A10–A0) = 00CH)
This register is a read only 10-bit register. However, R9–R8
are reserved bits, containing zeros. Bit R7 is a read only bit.
This bit should be masked in software on readback as its
value may be indeterminate. Therefore, the PLL R Register
may be treated as a 7-bit wide register. This register, to-
gether with the RSEL Bit in the PLL Control Register, con-
trols the reference divider of the on-board PLL.
Figure 44. Command Register (PCR) (PCR9–PCR0)
PCR9
PCR8
PCR7
PCR6
PCR2
PCR5
PCR4
PCR3
PCR1
PCR0
*
THESE BITS ARE READ-ONLY
RESERVED BITS.
A READ CYCLE WILL RETURN
ZEROS "00."
PCR5
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
S VALUE
PCR7 PCR6
(S1 S0)
0 0 0
0 1 1
1 0 2
1 1 3
RSEL ENABLE
PCR1
0 DISABLE
1 ENABLE
VSEL ENABLE
PCR2
0 DISABLE
1 ENABLE
PLL CONTROL
PCR0
0 DISABLE PLL
1 ENABLE PLL
F
OUT
PCR5 PCR4
(PSEL1 PSEL0)
0 0 VCO/1
0 1 VCO/2
1 0 VCO/4
1 1 VCO/8
RESERVED*
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