參數(shù)資料
型號(hào)： ADV7162KS220
廠商： ANALOG DEVICES INC
元件分類(lèi)： 顯示控制器
英文描述： 96-Bit, 220 MHz True-Color Video RAM-DAC
中文描述： 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 18/44頁(yè)
文件大?。?/td> 668K
代理商： ADV7162KS220
REV. 0
–18–
ADV7160/ADV7162
The SCKOUT signal is essentially the video memory shift con-
trol signal. It is stopped during the screen retrace. Figure 19 shows a
suggested frame buffer to ADV7160/ADV7162 interface. This is a
minimum chip solution and allows the ADV7160/ADV7162 con-
trol the overall graphics system clocking and synchronization.
LOADOUT
SCKOUT
ADV7160/
ADV7162
PIXEL
DATA
LOADIN
SCKIN
BLANK
VIDEO FRAME
BUFFER
Figure 19. ADV7160/ADV7162 Interface Using SCKIN
and SCKOUT
PLL
The on-board PLL can be used as an alternative clock source.
This eliminates the need for an external high speed clock gen-
erator such as a crystal oscillator. With the PLL, it is possible to
generate an internal clock whose frequency is a multiple of the PLL
reference frequency (PLL
REF
). Internal PLL operation is selected
by setting CR56 of Command Register 5 to Logic “1.” The PLL
registers can be programmed to set up the frequency required.
The block diagram of the Phase Locked Loop is shown in Fig-
ure 20. The blocks consist of a phase frequency detector, a
charge pump, a loop filter, a voltage controlled oscillator and a
programmable divider.
VOLTAGE
CONTROLLED
OSCILLATOR
CHARGE
PUMP
PHASE
DETECTOR
REFERENCE
DIVIDER
PLL
REF
F
PD
FEEDBACK
DIVIDER
F
VCO
O/P
DIVIDER
F
OUT
F
PD
Figure 20. PLL Block Diagram
The phase frequency detector drives the voltage controlled oscil-
lator (VCO), to a frequency that will cause the two inputs to the
phase frequency detector to be matched in frequency and phase.
The corresponding output of the VCO can be calculated as:
VCO
=
PLL
REF
Feedback Divider
Reference Divider
The Reference Divider is set by a combination of the contents of
the PLL R Register and the RSEL bit. The PLL R Register has
a resolution of 7 bits. It is programmed by setting the PLL R
Register located at Control Register address 00CH . The PLL
R Register can be set from 01H to 7FH. It should not be set to
00H. If this register contains 00H, then the PLL stops. There-
fore, the Reference Divider can be set from 3 to 129 in steps of
one, or from 130 to 258 in steps of two by setting the RSEL bit.
The RSEL bit is accessed by changing Bit PCR1 of the PLL
Control Register. The Feedback Divider is set by a combina-
tion of the contents of the PLL V Register, the VSEL bit and
the S value. The S value is set up in PCR7 and PCR6 of the
PLL Command Register. This S value allows a better resolu-
tion when setting the Feedback Divider value. The PLL V Reg-
ister has a resolution of 7 bits. It is programmed by setting the
PLL V Register located at Control Register address 00FH .The
PLL V Register can be set from 01H to 7FH. It should not be
set to 00H. If this register contains 00H, then the PLL stops.
Therefore the feedback divider can be set from 12 to 519 in
steps of one, or from 520 to 1038 in steps of two by setting the
VSEL bit. The VSEL bit is accessed by changing bit PCR2 of
the PLL Control Register. The P counter divides the output
from the oscillator by 1, 2, 4 or 8 as determined by PSEL1 and
PSEL0 which are set in bits PCR5 and PCR4 of the PLL Con-
trol Register. This post-scaler is useful in the generation of
lower frequencies as the VCO has been optimized for high
frequency operation.
(1 +
VSEL
)(4(V+2) + S)
(1 + RSEL)(R+2)
PLL
REF
F
VCO
VCO
VCO/2
VCO/4
VCO/8
PSEL1 PSEL0
F
OUT
F
OUT
F
VCO
F
VCO
/2
F
VCO/
4
F
VCO/
8
PSEL1
0
0
1
1
PSEL0
0
1
0
1
Figure 21. PLL Transfer Function
The transfer function of the PLL can be summarized by the
block diagram shown in Figure 21.
To optimize the performance of the on-board PLL, the follow-
ing criteria should be followed:
900 kHz
< PLL
REF
< 40 MHz
300 kHz
< F
PD
< 10 MHz
120 MHz
< F
VCO
< 260 MHz
For F
VCO
> 220 MHz, V
SEL
should be programmed to logic “0.”
Any lower frequency output can be achieved by using the output
divider.
A jitter performance graph as a function of both F
PD
and F
VCO
is
illustrated in Figure 22. It can be seen that jitter decreases with
increasing F
VCO
and also that jitter decreases with increasing
F
PD
. For each F
OUT
, the user should firstly maximize F
VCO
us-
ing the output divider and then pick PLL
REF
and reference di-
vide to maximize FPD. When generating multiple output
frequencies from one PLL
REF
value, an iterative process should
be used to find the PLL
REF
value that gives the best trade off be-
tween jitter performance and F
OUT
accuracy.
VCO FREQUENCY – MHz
250
050
300
100
150
200
250
200
150
100
50
FPD = 0.3MHz
FPD = 0.42MHz
FPD = 0.57MHz
FPD = 0.8MHz
FPD = 1.0MHz
FPD = 1.5MHz
FPD = 2.0MHz
FPD = 2.7MHz
FPD = 4.0MHz
FPD = 5.3MHz
JITTER MEASURED AT 15μs
R
Figure 22. PLL Jitter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7162KSZ140 制造商:Analog Devices 功能描述:DAC 3-CH Segment 10-bit 160-Pin MQFP
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ADV7170 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
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ADV7170KS 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management
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