參數(shù)資料
型號(hào): ADV7162KS220
廠商: ANALOG DEVICES INC
元件分類(lèi): 顯示控制器
英文描述: 96-Bit, 220 MHz True-Color Video RAM-DAC
中文描述: 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 25/44頁(yè)
文件大?。?/td> 668K
代理商: ADV7162KS220
ADV7160/ADV7162
REV. 0
–25–
Register Accesses
The MPU can write to or read from all of the ADV7160/
ADV7162’s registers. C0 and C1 determine whether the Mode
Register or Address Register is being accessed. Access to these
registers is direct. The Control Registers are accessed indi-
rectly. The Address Register must point to the desired Control
Register. Figure 33 and Figures 35 to 38 illustrate the structure
and protocol for device communication over the MPU port.
Databus
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Write Operation
Palette
Databus
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Read Operation
Palette
R/
W
C1
C0
Palette Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Register (Lo-Byte)
Write to Address Register (Hi-Byte)
Write Red Data (R9–R0)
Write Green Data (G9–G0)
Write Blue Data (B9–B0)
Write Red Data (R9–R0)
R/
W
C1
C0
Palette Read
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Register (Lo-Byte)
Write to Address Register (Hi-Byte)
Read Red Data (R9–R0)
Read Green Data (G9–G0)
Read Blue Data (B9–B0)
Read Red Data (R9–R0)
D2
D3
D4
D5
D6
D7
D0
D1
0
0
D2
D3
D4
D5
D6
D7
D0
D1
Figure 36. 8-Bit Databus Using 8-Bit DACs
Databus
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Write Operation
Palette
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Read Operation
Palette
D9
D3
D4
D5
D6
D7
D8
D0
D1
D2
Databus
D9
D3
D4
D5
D6
D7
D8
D0
D1
D2
R/
W
C1
C0
Palette Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Register (Lo-Byte)
Write to Address Register (Hi-Byte)
Write Red Data (R9–R0)
Write Green Data (G9–G0)
Write Blue Data (B9–B0)
Write Red Data (R9–R0)
R/
W
C1
C0
Palette Read
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Register (Lo-Byte)
Write to Address Register (Hi-Byte)
Read Red Data (R9–R0)
Read Green Data (G9–G0)
Read Blue Data (B9–B0)
Read Red Data (R9–R0)
Figure 37. 10-Bit Databus Using 10-Bit DACs
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Write Operation
Palette
Databus
R/
W
C1
C0
Palette Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Register (Lo-Byte)
Write to Address Register (Hi-Byte)
Write Red Data (R9–R0)
Write Green Data (G9–G0)
Write Blue Data (B9–B0)
Write Red Data (R9–R0)
R9
R3
R4
R5
R6
R7
R8
R0
R1
R2
Read Operation
Palette
R/
W
C1
C0
Palette Read
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
.
.
Write to Address Registe (Lo-Byte)
Write to Address Register (Hi-Byte)
Read Red Data (R9–R0)
Read Green Data (G9–G0)
Read Blue Data (B9–B0)
Read Red Data (R9–R0)
D9
D3
D4
D5
D6
D7
D8
D0
D1
D2
0
0
0
0
Databus
D9
D3
D4
D5
D6
D7
D8
D0
D1
D2
Figure 38. 10-Bit Databus Using 8-Bit DACS
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