參數(shù)資料
型號(hào)： XCB56364PV100
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 8-BIT, 100 MHz, OTHER DSP, PQFP112
封裝： QFP-112
文件頁數(shù)： 46/162頁
文件大?。?/td> 2405K
代理商： XCB56364PV100
Specifications
External Memory Expansion Port (Port A)
2-26
DSP56364 Advance Information
MOTOROLA
Notes:
1.
2.
3.
4.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56364.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
PC
equals 3
×
T
C
for read-after-read or write-after-write sequences).
BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ.
There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See
Figure 2-11
)
5.
6.
7.
Table 2-11 DRAM Page Mode Timings, Three Wait States
1, 2, 3
No.
Characteristics
Symbol
Expression
Min
Max
Unit
131
Page mode cycle time for two consecutive
accesses of the same direction
Page mode cycle time for mixed (read and
write) accesses
t
PC
2
×
T
C
1.25
×
T
C
40.0
35.0
—
—
ns
132
CAS assertion to data valid (read)
t
CAC
2
×
T
C
7.0
—
13.0
ns
133
Column address valid to data valid (read)
t
AA
3
×
T
C
7.0
—
23.0
ns
134
CAS deassertion to data not valid (read hold
time)
t
OFF
0.0
—
ns
135
Last CAS assertion to RAS deassertion
t
RSH
2.5
×
T
C
4.0
21.0
—
ns
136
Previous CAS deassertion to RAS deasser-
tion
t
RHCP
4.5
×
T
C
4.0
41.0
—
ns
137
CAS assertion pulse width
t
CAS
2
×
T
C
4.0
16.0
—
ns
138
Last CAS deassertion to RAS assertion
5
BRW[1:0] = 00
BRW[1:0] = 01
BRW[1:0] = 10
BRW[1:0] = 11
t
CRP
2.25
×
T
C
6.0
3.75
×
T
C
6.0
4.75
×
T
C
6.0
6.75
×
T
C
6.0
—
—
41.5
61.5
—
—
—
—
ns
139
CAS deassertion pulse width
t
CP
1.5
×
T
C
4.0
11.0
—
ns
140
Column address valid to CAS assertion
t
ASC
T
C
4.0
6.0
—
ns
Table 2-10 DRAM Page Mode Timings, Two Wait States
1, 2, 3, 7
(continued)
No.
Characteristics
Symbol
Expression
66 MHz
80 MHz
Unit
Min
Max
Min
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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