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參數(shù)資料
| 型號： | XCB56364PV100 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 8-BIT, 100 MHz, OTHER DSP, PQFP112 |
| 封裝： | QFP-112 |
| 文件頁數(shù)： | 31/162頁 |
| 文件大?。?/td> | 2405K |
| 代理商： | XCB56364PV100 |
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Specifications
Reset, Stop, Mode Select, and Interrupt Timing
MOTOROLA
DSP56364 Advance Information
2-11
29
Delay from
IRQA
,
IRQB
,
IRQD
,
NMI
asser-
tion to external memory (DMA source) access
address out valid
4.25
×
T
C
+ 2.0
44.0
—
ns
Notes:
1.
When using fast interrupts and IRQA, IRQB, and IRQD are defined as level-sensitive, timings 19 through
21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted
Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when
using Level-sensitive mode.
2.
This timing depends on several settings:
For PLL disable, using internal oscillator (PLL Control Register (PCTL) Bit 16 = 0) and oscillator disabled
during Stop (PCTL Bit 17 = 0), a stabilization delay is required to assure the oscillator is stable before
executing programs. In that case, resetting the Stop delay (OMR Bit 6 = 0) will provide the proper delay.
While it is possible to set OMR Bit 6 = 1, it is not recommended and these specifications do not guarantee
timings for that case.
For PLL disable, using internal oscillator (PCTL Bit 16 = 0) and oscillator enabled during Stop (PCTL Bit
17=1), no stabilization delay is required and recovery time will be minimal (OMR Bit 6 setting is ignored).
For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time
will be defined by the PCTL Bit 17 and OMR Bit 6 settings.
For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to
1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when
the last of these two events occurs. The stop delay counter completes count or PLL lock procedure
completion.
PLC value for PLL disable is 0.
The maximum value for ET
C
is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100
MHz it is 4096/100 MHz = 40
μ
s). During the stabilization period, T
C
, T
H,
and T
L
will not be constant, and
their width may vary, so timing may vary as well.
3.
Periodically sampled and not 100% tested
4.
For an external clock generator, RESET duration is measured during the time in which RESET is asserted,
V
CC
is valid, and the EXTAL input is active and valid.
For internal oscillator, RESET duration is measured during the time in which RESET is asserted and V
CC
is
valid. The specified timing reflects the crystal oscillator stabilization time after power-up. This number is
affected both by the specifications of the crystal and other components connected to the oscillator and
reflects worst case conditions.
When the V
CC
is valid, but the other “required RESET duration” conditions (as specified above) have not
been yet met, the device circuitry will be in an uninitialized state that can result in significant power
consumption and heat-up. Designs should minimize this state to the shortest possible duration.
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
6
(continued)
No.
Characteristics
Expression
Min
Max
Unit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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