
Specifications
External Memory Expansion Port (Port A)
MOTOROLA
DSP56364 Advance Information
2-23
143
WR deassertion to CAS asser-
tion
t
RCS
0.75
×
T
C
3.8
33.7
—
21.2
—
ns
144
CAS deassertion to WR asser-
tion
t
RCH
0.25
×
T
C
3.7
8.8
—
4.6
—
ns
145
CAS assertion to WR deasser-
tion
t
WCH
0.5
×
T
C
4.2
20.8
—
12.5
—
ns
146
WR assertion pulse widt
h
t
WP
1.5
×
T
C
4.5
70.5
—
45.5
—
ns
147
Last WR assertion to RAS
deassertion
t
RWL
1.75
×
T
C
4.3
83.2
—
54.0
—
ns
148
WR assertion to CAS deasser-
tion
t
CWL
1.75
×
T
C
4.3
83.2
—
54.0
—
ns
149
Data valid to CAS assertion
(Write)
t
DS
0.25
×
T
C
4.0
8.5
—
4.3
—
ns
150
CAS assertion to data not valid
(write)
t
DH
0.75
×
T
C
4.0
33.5
—
21.0
—
ns
151
WR assertion to CAS asser-
tion
t
WCS
T
C
4.3
45.7
—
29.0
—
ns
152
Last RD assertion to RAS
deassertion
t
ROH
1.5
×
T
C
4.0
71.0
—
46.0
—
ns
153
RD assertion to data valid
t
GA
T
C
7.5
—
42.5
—
25.8
ns
154
RD deassertion to data not
valid
5
t
GZ
0.0
—
0.0
—
ns
155
WR assertion to data active
0.75
×
T
C
0.3
37.2
—
24.7
—
ns
156
WR deassertion to data high
impedance
0.25
×
T
C
—
12.5
—
8.3
ns
Notes:
1.
2.
3.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
PC
equals 2
×
T
C
for read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each
DRAM out-of-page access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
OFF
and not t
GZ
.
Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See
Figure 2-14
.).
4.
5.
6.
Table 2-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)
1, 2, 3
No.
Characteristics
Symbol
Expression
20 MHz
6
30 MHz
6
Unit
Min
Max
Min
Max
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.