參數(shù)資料
型號: XCB56364PV100
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 8-BIT, 100 MHz, OTHER DSP, PQFP112
封裝: QFP-112
文件頁數(shù): 38/162頁
文件大小: 2405K
代理商: XCB56364PV100
Specifications
External Memory Expansion Port (Port A)
2-18
DSP56364 Advance Information
MOTOROLA
113
RD deassertion time
0.75
×
T
C
4.0
[1
WS
3]
3.5
ns
1.75
×
T
C
4.0
[4
WS
7]
13.5
ns
2.75
×
T
C
4.0
[WS
8]
23.5
ns
114
WR deassertion time
0.5
×
T
C
4.0
[WS = 1]
1.0
ns
T
C
2.0
[2
WS
3]
6.0
ns
2.5
×
T
C
4.0
[4
WS
7]
21.0
ns
3.5
×
T
C
4.0
[WS
8]
31.0
ns
115
Address valid to RD assertion
0.5
×
T
C
4.0
1.0
ns
116
RD assertion pulse width
(WS + 0.25)
×
T
C
4.0
8.5
ns
117
RD deassertion to address not
valid
0.25
×
T
C
2
.0
[1
WS
3]
0.5
ns
1.25
×
T
C
2.0
[4
WS
7]
10.5
ns
2.25
×
T
C
2.0
[WS
8]
20.5
ns
118
TA setup before RD or WR
deassertion
4
0.25
×
T
C
+ 2.0
4.5
ns
119
TA hold after RD or WR deasser-
tion
0
ns
Notes:
1.
2.
3.
4.
WS is the number of wait states specified in the BCR.
Timings 100, 107 are guaranteed by design, not tested.
All timings for 100 MHz are measured from 0.5
·
Vcc to .05
·
Vcc
In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to
remain active
Table 2-8 SRAM Read and Write Accesses
3
(continued)
No.
Characteristics
Symbol
Expression
1
Min
Max
Unit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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