參數(shù)資料
型號(hào): XCB56364PV100
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 8-BIT, 100 MHz, OTHER DSP, PQFP112
封裝: QFP-112
文件頁數(shù): 30/162頁
文件大?。?/td> 2405K
代理商: XCB56364PV100
Specifications
Reset, Stop, Mode Select, and Interrupt Timing
2-10
DSP56364 Advance Information
MOTOROLA
26
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)
2, 3
PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is enabled
(OMR Bit 6 = 0)
PLC
×
ET
C
×
PDF + (128K
PLC/2)
×
T
C
13.6
ms
PLL is not active during Stop (PCTL Bit
17 = 0) and Stop delay is not enabled
(OMR Bit 6 = 1)
PLC
×
ET
C
×
PDF + (20.5
±
0.5)
×
T
C
12.3
ms
PLL is active during Stop (PCTL Bit 17 =
1) (implies no Stop delay)
5.5
×
T
C
55.0
ns
27
Interrupt Requests Rate
ESAI, SCI
12T
C
120.0
ns
DMA
8T
C
80.0
ns
IRQ
,
NMI
(edge trigger)
8T
C
80.0
ns
IRQ
,
NMI
(level trigger)
12T
C
120.0
ns
28
DMA Requests Rate
Data read from ESAI, SCI
6T
C
60.0
ns
Data write to ESAI, SCI
7T
C
70.0
ns
IRQ
,
NMI
(edge trigger)
3T
C
30.0
ns
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
6
(continued)
No.
Characteristics
Expression
Min
Max
Unit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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