參數(shù)資料
型號： USB-I2C/LIN-CONV-Z
廠商： Analog Devices Inc
文件頁數(shù)： 27/104頁
文件大?。?/td> 0K
描述： USB TO I2C/LIN CONV BOARD
標(biāo)準(zhǔn)包裝： 1
附件類型： 適配器板
適用于相關(guān)產(chǎn)品： ARM7TDMI?
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 29 of 104
Pin No.
Mnemonic
Description
18
P4.6/AD14/PLAO[14]
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
19
P4.7/AD15/PLAO[15]
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
20
BM/P0.0/CMPOUT/PLAI[7]/MS0
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM
is low at reset and execute code if BM is pulled high at reset through a 1 k resistor/General-
Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array
Input Element 7/External Memory Select 0.
21
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/
Power-On Reset Output/Programmable Logic Array Output Element 3.
22
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
23
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
24
P0.2/PWM2L/BHE
General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
Byte High Enable.
25
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
26
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
27
LVDD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 F
capacitor to DGND only.
28
DGND
Ground for Core Logic.
29
P3.0/AD0/PWM0H/PLAI[8]
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-Side
Output/Programmable Logic Array Input Element 8.
30
P3.1/AD1/PWM0L/PLAI[9]
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-Side
Output/Programmable Logic Array Input Element 9.
31
P3.2/AD2/PWM1H/PLAI[10]
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-Side
Output/Programmable Logic Array Input Element 10.
32
P3.3/AD3/PWM1L/PLAI[11]
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-Side
Output/Programmable Logic Array Input Element 11.
33
P2.4/PWM0H/MS0
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
34
P0.3/TRST/A16/ADCBUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output.
35
P2.5/PWM0L/MS1
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
36
P2.6/PWM1H/MS2
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
37
RST
Reset Input, Active Low.
38
P3.4/AD4/PWM2H/PLAI[12]
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-Side
Output/Programmable Logic Array Input 12.
39
P3.5/AD5/PWM2L/PLAI[13]
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-Side
Output/Programmable Logic Array Input Element 13.
40
IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/
External Memory Select 1.
41
IRQ1/P0.5/ADCBUSY/PLAO[2]/MS2
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External
Memory Select 2.
42
P2.0/SPM9/PLAO[5]/CONVSTART
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
43
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
44
XCLKO
Output from the Crystal Oscillator Inverter.
45
XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
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