參數(shù)資料
型號(hào)： USB-I2C/LIN-CONV-Z
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 100/104頁(yè)
文件大小： 0K
描述： USB TO I2C/LIN CONV BOARD
標(biāo)準(zhǔn)包裝： 1
附件類(lèi)型： 適配器板
適用于相關(guān)產(chǎn)品： ARM7TDMI?
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 95 of 104
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC7019/20/21/22/24/25/26/27/28/29. For LVDD below 2.35 V
typical, the internal POR holds the part in reset. As LVDD rises
above 2.35 V, an internal timer times out for, typically, 128 ms
before the part is released from reset. The user must ensure that
the power supply IOVDD reaches a stable 2.7 V minimum level
by this time. Likewise, on power-down, the internal POR holds
the part in reset until LVDD drops below 2.35 V.
Figure 94 illustrates the operation of the internal POR in detail.
TYPICAL SYSTEM CONFIGURATION
A typical ADuC7020 configuration is shown in Figure 95. It
summarizes some of the hardware considerations discussed in
the previous sections. The bottom of the CSP package has an
exposed pad that must be soldered to a metal plate on the board
for mechanical reasons. The metal plate of the board can be
connected to ground.
IOVDD
3.3V
2.6V
2.35V TYP
128ms TYP
LVDD
POR
MRST
0.12ms TYP
04
955
-050
Figure 94. Internal Power-On Reset Operation
NOT CONNECTED IN THIS EXAMPLE
30
29
28
27
26
25
XCLKI
24
XCLKO
23
22
21
1
2
3
GNDREF
4
DAC0
5
6
7
8
TMS
9
TDI
10
P0.0
40
39
38
AD
C0
37
AV
DD
36
AG
ND
35
V
RE
F
34
33
P1
.0
32
P1
.1
31
11
12
13
TD
O
TC
K
14
IOG
N
D
15
IOV
DD
16
LV
DD
DG
ND
17
18
TR
S
T
19
RS
T
20
DVDD
1k
10
ADuC7020
0.01F
+
–
AVDD
0.47F
TDO
TCK
TMS
TDI
TRST
JT
A
G
CO
NNE
CT
O
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVDD
10
0k
10
0k
10
0k
DVDD
32.768kHz
0.47F
1k
0.1F
10F
1.5
270
DVDD
AVDD
ADP3333-3.3
IN
OUT
SD
GND
1
C1+
2
V+
3
C1–
4
C2+
5
C2–
6
V–
7
T2OUT
8
R2IN
ADM3202
RS232 INTERFACE*
* EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS
PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.
STANDARD D-TYPE
SERIAL COMMS
CONNECTOR TO
PC HOST
16
VCC
15
GND
14
T1OUT
13
R1IN
12
R1OUT
11
T1IN
10
T2IN
9
R2OUT
1
2
3
4
5
6
7
8
9
04
95
5-
05
1
Figure 95. Typical System Configuration
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