CHAPTER 3 CPU FUNCTION
91
Preliminary User’s Manual U16031EJ2V1UD
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Bit Units for Manipulation
Address
Function Register Name
Symbol
R/W
1 Bit
8 Bits 16 Bits
After Reset
FFFFF42CH
Port 6 mode register
PM6
R/W
√√
FFH
FFFFF42EH
Port 7 mode register
PM7
R/W
√√
FFH
FFFFF442H
Port 1 mode control register
PMC1
R/W
√√
00H
FFFFF444H
Port 2 mode control register
PMC2
R/W
√√
01H
FFFFF44AH
Port 5 mode control register
PMC5
R/W
√√
00H
FFFFF44CH
Port 6 mode control register
PMC6
R/W
√√
00H
FFFFF44EH
Port 7 mode control register
PMC7
R/W
√√
00H
FFFFF462H
Port 1 function control register
PFC1
R/W
√√
00H
FFFFF464H
Port 2 function control register
PFC2
R/W
√√
00H
FFFFF46AH
Port 5 function control register
PFC5
R/W
√√
00H
FFFFF46CH
Port 6 function control register
PFC6
R/W
√√
00H
FFFFF46EH
Port 7 function control register
PFC7
R/W
√√
00H
FFFFF480H
Bus cycle type configuration register 0
BCT0
R/W
√
8888H
FFFFF482H
Bus cycle type configuration register 1
BCT1
R/W
√
8888H
FFFFF484H
Data wait control register 0
DWC0
R/W
√
7777H
FFFFF486H
Data wait control register 1
DWC1
R/W
√
7777H
FFFFF488H
Bus cycle control register
BCC
R/W
√
FFFFH
FFFFF48AH
Address setup wait control register
ASC
R/W
√
FFFFH
FFFFF48CH
Bus cycle period control register
BCP
R/W
√√
00H
FFFFF48EH
Local bus sizing control register
LBS
R/W
√
5555H/AAAAH
Note
FFFFF490H
Line buffer control register 0
LBC0
R/W
√
0000H
FFFFF492H
Line buffer control register 1
LBC1
R/W
√
0000H
FFFFF494H
DMA flyby transfer wait control register
FWC
R/W
√
7777H
FFFFF496H
DMA flyby transfer idle control register
FIC
R/W
√
3333H
FFFFF498H
Bus mode control register
BMC
R/W
√
00H
FFFFF49AH
Page ROM configuration register
PRC
R/W
√
7000H
FFFFF4A4H
SDRAM configuration register 1
SCR1
R/W
√
30C0H
FFFFF4A6H
SDRAM refresh control register 1
RFS1
R/W
√
0000H
FFFFF4ACH
SDRAM configuration register 3
SCR3
R/W
√
30C0H
FFFFF4AEH
SDRAM refresh control register 3
RFS3
R/W
√
0000H
FFFFF4B0H
SDRAM configuration register 4
SCR4
R/W
√
30C0H
FFFFF4B2H
SDRAM refresh control register 4
RFS4
R/W
√
0000H
FFFFF4B8H
SDRAM configuration register 6
SCR6
R/W
√
30C0H
FFFFF4BAH
SDRAM refresh control register 6
RFS6
R/W
√
0000H
FFFFF540H
Timer D0
TMD0
R
√
0000H
Note 32-bit mode: AAAAH
16-bit mode: 5555H
For details of 32-bit mode and 16-bit mode, refer to 3.3.1 Operating modes.