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| 型號(hào)： | UPD703111GM-15-UEU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, FINE PITCH, PLASTIC, LQFP-176 |
| 文件頁(yè)數(shù)： | 190/238頁(yè) |
| 文件大小： | 6598K |
| 代理商： | UPD703111GM-15-UEU |
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CHAPTER 2 PIN FUNCTIONS
55
Preliminary User’s Manual U16031EJ2V1UD
(7) PCT0 to PCT5, PCT7 (Port CT) 3-state I/O
PCT0 to PCT5 and PCT7 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CT mode control
register (PMCCT).
(a) Port mode
PCT0 to PCT5 and PCT7 can be set to input or output in 1-bit units using the port CT mode register
(PMCT).
(b) Control mode
PCT0 to PCT5 and PCT7 can be set to port/control mode in 1-bit units using the PMCCT register.
(i)
LLWR (Lower lower byte write strobe) 3-state output
This is a strobe signal output pin that shows whether the bus cycle currently being executed is a
write cycle for the SRAM, external ROM, or external peripheral I/O area.
For the data bus, the lowest byte (D0 to D7) becomes valid. If the bus cycle is a lowest memory
write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes
inactive at the falling edge of the BUSCLK signal in the T2 state.
(ii) LUWR (Lower upper byte write strobe) 3-state output
This is a strobe signal output pin that shows whether the bus cycle currently being executed is a
write cycle for the SRAM, external ROM, or external peripheral I/O area.
For the data bus, the third byte (D8 to D15) becomes valid. If the bus cycle is a third byte memory
write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes
inactive at the falling edge of the BUSCLK signal in the T2 state.
(iii) ULWR (Upper lower byte write strobe) 3-state output
This is a strobe signal output pin that shows whether the bus cycle currently being executed is a
write cycle for the SRAM, external ROM, or external peripheral I/O area.
For the data bus, the second byte (D16 to D23) becomes valid. If the bus cycle is a second byte
memory write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and
becomes inactive at the falling edge of the BUSCLK signal in the T2 state.
(iv) UUWR (Upper upper byte write strobe) 3-state output
This is a strobe signal output pin that shows whether the bus cycle currently being executed is a
write cycle for the SRAM, external ROM, or external peripheral I/O area.
For the data bus, the highest byte (D24 to D31) becomes valid. If the bus cycle is a highest memory
write, it becomes active at the falling edge of the BUSCLK signal in the T1 state and becomes
inactive at the falling edge of the BUSCLK signal in the T2 state.
(v) LLBE (Lower lower byte enable) 3-state output
This is a signal output pin that enables the lowest byte (D0 to D7) of the external data bus.
(vi) LUBE (Lower upper byte enable) 3-state output
This is a signal output pin that enables the third byte (D8 to D15) of the external data bus.
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