參數(shù)資料
型號(hào): UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁(yè)數(shù): 40/81頁(yè)
文件大?。?/td> 323K
代理商: UJA1061
2004 Mar 22
40
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
Notes
1.
This flag is cleared automatically upon each overflow event. It has to be set in software each time the interrupt
behaviour is required (fail-safe behaviour).
If V2 or V3 is shut down due to a short-circuit, or activation of V2 or V3 fails due to a short-circuit, the interrupt is
forced. V2 can be activated again by clearing CTC (CAN Transmitter Control), setting CAN mode or via a wake-up
event on CAN. V3 can be activated setting bit V3C to a value other than ‘00’.
2.
1
CANIE
CAN Interrupt Enable
1
0
1
0
CAN-bus event results in a wake-up interrupt
CAN-bus event results in a reset
LIN-bus event results in a wake-up interrupt
LIN-bus event results in a reset
0
LINIE
LIN Interrupt Enable
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
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參數(shù)描述
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