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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片 |
| 文件頁數(shù)： | 39/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
39
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14.5
I
NTERRUPT ENABLE REGISTER
This register, which can be written to only in Normal and Standby modes, allows setting/enabling certain interrupt events
for the UJA1061
Table 6
IE - Interrupt Enable register (address 01) bit description
BIT
SYMBOL
DESCRIPTION
VALUE
FUNCTION
15, 14
13
A1, A0
RRS
register address
Read Register Select
01
1
0
1
read Interrupt Enable register
read the Interrupt Register (INT)
read the Interrupt Enable Feedback register (IEF)
read the register selected by RRS without writing to
Interrupt Enable register
read the register selected by RRS and write to Interrupt
Enable register
a watchdog overflow during Standby causes an interrupt
instead of a reset event
no interrupt forced upon overflow; a reset is forced instead
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; within Start-up and Restart mode, a
reset is performed instead of an interrupt
no interrupt forced; SPI access is ignored if wrong number
of cycles is applied (more than, or less than 16)
falling edge at SENSE forces an interrupt
no interrupt forced
detection of a short-circuit at V2 or V3 forces an interrupt
no interrupt forced
any change of the CAN Failure status forces an interrupt
no interrupt forced
any change of the LIN Failure status forces an interrupt
no interrupt forced
a negative edge at WAKE generates an interrupt in
Normal, Flash or Standby mode
a negative edge at WAKE generates a reset in Standby
mode
reserved for future use; should always be set to logic 0 in
order to secure compatibility with future functions which will
be activated by a logic 1
12
RO
Read Only
0
11
WTIE
Watchdog Time-out
Interrupt Enable
(1)
1
0
1
10
OTIE
Over-Temperature
Interrupt Enable
0
1
9
GSIE
GroundShiftInterrupt
Enable
0
1
8
SPIFIE
SPI clock count
Failure Interrupt
Enable
0
7
BATFIE
BAT Failure Interrupt
Enable
1
0
1
0
1
0
1
0
1
6
V2V3FIE
V2/V3 Failure
Interrupt Enable
(2)
5
CANFIE
CAN Failure Interrupt
Enable
4
LINFIE
LIN Failure Interrupt
Enable
3
WIE
WAKE Interrupt
Enable
0
2
reserved
0
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