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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎芯片 |
| 文件頁數(shù)： | 14/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
14
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.4.1
W
ATCHDOG START
-
UP BEHAVIOUR
Within Start-up and Restart mode of the UJA1061, the
watchdog offers its start-up behaviour. In this mode the
watchdog monitors pin RSTN (input) to check whether it
becomes released or is clamped externally. Any time
pin RSTN stays LOW longer than the reset monitoring
period, this is interpreted as a clamping situation and the
corresponding mode change of the UJA1061 is performed.
Once the reset pin has been released within the reset
monitoring period the start-up period begins (see Fig.4).
If the microcontroller does not initialize the watchdog
within this time frame, the watchdog restarts the system
via the reset output and enters Restart mode. The whole
procedurewiththeresetmonitoringperiodandthestart-up
period repeats. If pin RSTN is LOW for too long, or the
microcontroller did not initialize the watchdog within the
time, Fail-safe mode will be entered.
If pin RSTN has been released and the initialization phase
is entered, a falling edge on pin RSTN results immediately
in a transition from Start-up to Restart mode, or from
Restart to Fail-safe mode (fail-safe behaviour in case of
chattering reset events).
If pin RSTN is held LOW internally by the UJA1061, due to
a low voltage situation at pin V1 caused, for example, by a
short-circuit, the watchdog again monitors this time. After
the reset monitoring period, Fail-safe mode is entered and
pin V1 is disabled.
So, independently from the cause of a reset event, the
watchdog starts the reset monitoring period whenever
pin RSTN is pulled LOW.
During the start-up period, the UJA1061 accepts write
access to the General Purpose registers, the Special
Mode register (once after the first supply connection only)
and the Mode register only.
mce625
start-up period
RST monitoring period
start-up period
RST monitoring period
(1)
(2)
(3)
(4)
(5)
pin RSTN
input
watchdog
period
< 256 ms
Start-up
Restart
< 256 ms
< 256 ms
< 256 ms
Fig.4 Reset monitoring and start-up period.
(1) UJA1061 releases pin RSTN after 1 ms or 20 ms.
(2) External hardware releases pin RSTN.
(3) Watchdog initialization fails.
(4) 20 ms reset period.
(5) External hardware releases pin RSTN.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UJA1061_10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip |
| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
| UJA1061TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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