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參數(shù)資料
| 型號： | UJA1061 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low speed CAN/LIN system basis chip |
| 中文描述： | 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片 |
| 文件頁數(shù)： | 31/81頁 |
| 文件大?。?/td> | 323K |
| 代理商： | UJA1061 |
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2004 Mar 22
31
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.14
SPI register mapping
Any control bit which might be set in software is readable
by the application. This allows software debugging as well
as control algorithms to be implemented. There is also a
read-only access possible without actively writing to an
SPI register.
The following constraints are implemented in the register
mapping:
The number of clock cycles during one SPI access has
to be 16
Watchdog period and mode setting is performed within
thesameaccesscycle;thisallowsamodechangeofthe
UJA1061 with simultaneously changing the period and
the mode of the watchdog
Each register carries only 12 functional bits; 4 bits are
used for register selection and read/write definition.
6.14.1
R
EGISTER OVERVIEW
Since the SPI interface is bidirectional, each write access
automatically implies a register read access to one of the
internal registers, see Table 2. In order to allow a register
to be read without writing data to it, a read-only feature is
incorporated.
A 4-bit header defines any SPI access to one of the
registers. The first two bits, address bits A1 and A0, define
the register address. These are followed by the read
register select bit RRS that defines the feedback register
for this access. The fourth bit RO allows a ‘read only’
access to one of the feedback registers.
Depending on the mode, some registers can be written to
and/or read from, and some not. During the first watchdog
initialization phase, directly after the first battery
connection, the special mode bits register can be set only
once. After this special mode register access, or any other
access to the UJA1061, these bits cannot be accessed
again. This special mode register is used for entering the
Software Development mode. The Software Development
mode bit SDM, present in the system configuration
register, can be read out and also reset all the time in
Normal operating mode and Standby mode.
The UJA1061 has two 12-bit General Purpose registers
with no prescribed bit definition. During power-up the bits
of General Purpose register 0 (GP0) will be loaded with a
‘Device Identification Code’ consisting of the SBC type
and SBC version. The bits of General Purpose register 1
(GP1) will be reset after power-up. All bits of GP0 and GP1
cannot be changed any more by the UJA1061, with the
exceptionofbit11ofregister GP0whichindicateswhether
the content of register GP0 is the ‘Device Identification
Code’ (bit 11 = logic 1), or used already as an extra
register by the microcontroller (bit 11 = logic 0). Only the
application microcontroller can change the other 23 bits
during the Start-up mode, Restart mode or Flash
Programming mode. The microcontroller can read these
two registers all the time. The purpose of the General
Purpose register is to give the microcontroller the
possibility of storing certain system status information that
cannot be held within the microcontroller memory. This is
very useful for applications making use of the Sleep mode
(unpowered microcontroller) saving important data bits for
the next operating cycle.
Furthermorethesetworegisterscanbeusedforenhanced
system diagnosis and fail-safe features. If, for example, a
fault in the memory of the microcontroller always causes
thesameresetduetoasoftwarecrash,themicrocontroller
can count these events and write the corresponding
information into these register bits. The reset source
register bits offer the corresponding information about the
root cause of the problem. Thus, the microcontroller can
take action depending on the number of identical resets
and so prevent an ECU from permanent system crash
situations consuming permanently high power. Thus, the
general purpose registers offer a kind of ‘non volatile
memory’ to the microcontroller since the UJA1061 is
always powered from the battery line, independently from
the supply of the microcontroller which could possibly be
without power from time to time.
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相關(guān)代理商/技術(shù)參數(shù) |
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| UJA1061TW/3V0,512 | 制造商:NXP Semiconductors 功能描述: |
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| UJA1061TW/3V3/C/T, | 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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