參數(shù)資料
型號： UJA1061
廠商： NXP Semiconductors N.V.
英文描述： Low speed CAN/LIN system basis chip
中文描述： 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù)： 16/81頁
文件大?。?/td> 323K
代理商： UJA1061
2004 Mar 22
16
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
6.4.3
W
ATCHDOG TIME
-
OUT BEHAVIOUR
Whenever the UJA1061 operates in Standby mode, in
Sleep mode or in Flash mode, the watchdog is operated in
Time-out mode. The watchdog has to be triggered within
the actual programmed period time (see Fig.6). The
Time-out mode can be used to provide cyclic wake-up
events to the host microcontroller during Low-power
modes.
In Standby and in Flash mode the nominal periods can be
changed with any SPI access to the mode register. Since
inSleepmoderegulator V1isoffandthe microcontrolleris
not powered, no further change of the time-out period is
possible.
Any wrong mode register code access results in an
immediate system reset, entering Start-up mode.
6.4.4
W
ATCHDOG
OFF
BEHAVIOUR
Within Standby and Sleep mode, the watchdog OFF
behaviourcanbeselectedinordertodisablethewatchdog
entirely.
If the watchdog is triggered with the watchdog OFF code
while the UJA1061 is in Standby Mode, or while the
UJA1061 enters Standby mode, the V1 current monitoring
function stays disabled for a period of time equal to the
previous or the default (4096 ms) watchdog period. The
default period is selected if the Standby mode is entered
directly with Watchdog OFF mode. After that period the
current monitoring is enabled. Then the behaviour of the
UJA1061 upon a too-high V1 current depends on the
setting of the V1CMC bit within the System Configuration
register. If bit V1CMC is set (reset option) a too-high V1
current causes immediatelyareset. Ifbit V1CMC isnotset
(watchdog restart option), the watchdog starts a new
period without the possibility to disable it except by
triggering it again with the watchdog OFF code. If the
watchdog OFF code is chosen the watchdog time-out
interrupthasnofunction.Ifthewatchdogoffbehaviourhas
been entered successfully and later on pin V1 current
increases again, the watchdog starts operating with the
previously programmed time-out period.
In case Standby mode is entered directly out of Normal
mode with watchdog off behaviour coding, the watchdog
keeps running with its maximum time period until pin V1
current falls below the threshold. If the current increases
again, the maximum period is used again.
If Sleep mode is entered together with the watchdog OFF
behaviour, the UJA1061 immediately forces pin RSTN to
LOWlevel.Inparallel,pin V1isdisabledandthewatchdog
is stopped.
handbook, full pagewidth
MCE627
trigger
via SPI
earliest
possible
trigger
point
latest
possible
trigger
point
trigger restarts period
(with different duration if
desired)
new period
trigger range
trigger range
time-out
time-out
period
Fig.6 Watchdog triggering using Time-out mode.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UJA1061_10 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Fault-tolerant CAN/LIN fail-safe system basis chip
UJA1061TW/3V0,512 制造商:NXP Semiconductors 功能描述:
UJA1061TW/3V0512 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP
UJA1061TW/3V3/C/T, 功能描述:CAN 接口集成電路 FT CAN/LIN fail-safe system basis chip RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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