參數(shù)資料
型號: UJA1061
廠商: NXP Semiconductors N.V.
英文描述: Low speed CAN/LIN system basis chip
中文描述: 低高速CAN / LIN系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 22/81頁
文件大小: 323K
代理商: UJA1061
2004 Mar 22
22
Philips Semiconductors
Objective specification
Low speed CAN/LIN system basis chip
UJA1061
mce630
ON-LINE
V2: ON/OFF
(V2D)
transmitter: OFF
receiver: ON/LP (V2D)
pin RXDC: wake-up
flip flop
CANL bias: V2/
floating/(V2D)
ACTIVE
V2: ON/OFF (V2D)
transmitter: ON/OFF
(CTC)
receiver: ON/LP (V2D)
pin RXDC:
bitstream/HIGH (V2D)
CANL bias: V2/
floating/(V2D)
OFF-LINE
V2: OFF
transmitter: OFF
receiver: LP
pin RXDC: V1
CANL bias: LP/
floating/(V2D)
SELECTIVE
SLEEP
V2: ON/OFF
(V2D)
transmitter: OFF
receiver: ON/LP (V2D)
pin RXDC: V1
CANL bias: V2/
floating/(V2D)
event
action
Power-on
Global wake-up CAN message
detected
Wake-up flip flop set
CPNC set to logic 0
CM = logic 0
AND CPNC = logic 0
CM = logic 1
CPNC set to logic 0
CAN mode = logic 0
AND CPNC = logic 1
CM = logic 1
Wake-up flip flop
cleared
CM = logic 1
CPNC set to logic 0
CAN wake-up filter passed
AND CPNC = logic 0
Wake-up flip flop set
CAN wake-up
filter passed
Wake-up
flip flop set
CPNC = logic 1
Wake-up flip flop cleared
CPNC set
to logic 0
no activity t > t
off-line
Wake-up flip flop cleared
no activity t > toff-line
ACTIVE
CAN mode = logic 1
AUTO
CAN mode = logic 0
CAN wake-up filter passed
AND CPNC = logic 1
Fig.9 States of the CAN transceiver.
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