參數(shù)資料
型號(hào): UDA1384
廠商: NXP Semiconductors N.V.
英文描述: Multichannel audio coder-decoder
中文描述: 多聲道音頻編碼解碼器
文件頁(yè)數(shù): 44/55頁(yè)
文件大?。?/td> 276K
代理商: UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
44 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
[1]
The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series
resistor.
[2]
The input voltage to the ADC scales proportionally with the power supply voltage.
15.1 Timing
Single-ended mode
V
o(rms)
V
o
output voltage (RMS value)
output voltage unbalance between
channels
(THD + N)/S total harmonic
distortion-plus-noise to signal ratio
at 0 dBFS digital input
-
-
1.0
< 0.1
-
-
V
dB
at 0 dBFS
at
20 dBFS
at
60 dBFS; A-weighted
code = 0; A-weighted
-
-
-
-
-
88
85
45
105
110
-
-
-
-
-
dB
dB
dB
dB
dB
S/N
α
cs
signal-to-noise ratio
channel separation
Table 66:
V
DDD
= V
DDA(AD)
= V
DDA(DA)
= 3.3 V; f
i
= 1 kHz; T
amb
= 25
°
C; R
L
= 22 k
; sampling frequency f
s
= 48 kHz; all voltages
referenced to ground (pins V
SS
); unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
Table 67:
V
DDD
= V
DDA(AD)
= V
DDA(AD)
= 2.7 V to 3.6 V; T
amb
=
20
°
C to +85
°
C; typical timing specified at sampling frequency
f
s
= 48 kHz; unless otherwise specified.
Symbol
Parameter
Conditions
System clock (see
Figure 16
)
T
sys
system clock cycle time
f
sys
= 256f
s
f
sys
= 384f
s
f
sys
= 512f
s
f
sys
= 768f
s
t
CWL
system clock LOW time
f
sys
< 19.2 MHz
f
sys
19.2 MHz
t
CWH
system clock HIGH time
f
sys
< 19.2 MHz
f
sys
19.2 MHz
I
2
S-bus interface
Serial data of audio ADC and DAC (see
Figure 17
)
f
BCK
audio bit clock frequency
T
cy(BCK)
BCK cycle time
t
BCKH
bit clock HIGH time
t
BCKL
bit clock LOW time
t
r
rise time
t
f
fall time
t
su(WS)
word select set-up time
t
h(WS)
word select hold time
t
su(DATAI)
data input set-up time
t
h(DATAI)
data input hold time
t
h(DATAO)
data output hold time
Timing
Min
Typ
Max
Unit
[1]
35
81
54
41
27
-
-
-
-
780
520
390
260
0.7T
sys
0.6T
sys
0.7T
sys
0.6T
sys
ns
ns
ns
ns
ns
ns
ns
ns
[1]
23
[1]
17
[1]
17
0.3T
sys
0.4T
sys
0.3T
sys
0.4T
sys
[2]
-
-
-
-
-
-
-
-
-
-
-
-
12.8
78
-
-
20
20
-
-
-
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
30
30
-
-
10
10
10
10
0
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