參數(shù)資料
型號: UDA1384
廠商: NXP Semiconductors N.V.
英文描述: Multichannel audio coder-decoder
中文描述: 多聲道音頻編碼解碼器
文件頁數(shù): 36/55頁
文件大?。?/td> 276K
代理商: UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
36 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
11.9 DAC channel 1 to channel 6 settings
All the DAC features which are written in register 11h are copied into the odd channel
registers.
All the DAC features which are written in register 11h are copied into the even channel
registers, except the bits ICS[1:0].
11.10 DAC mixing channel settings
All the DAC features which are written in register 11h are copied into the odd mixing
channel registers, except the bits DE[2:0].
Table 48:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DAC channel 1, 3 and 5 registers (address 12h, 14h and 16h) bit allocation
15
14
13
12
ICS1
ICS0
DE2
DE1
0
0
0
0
read and write
7
6
5
4
VC7
VC6
VC5
VC4
0
0
0
0
read and write
11
DE0
0
10
PD
0
9
8
MT
0
QM
0
3
2
1
0
VC3
0
VC2
0
VC1
0
VC0
0
Table 49:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DAC channel 2, 4 and 6 registers (address 13h, 15h and 17h) bit allocation
15
14
13
12
-
-
DE2
DE1
0
0
0
0
read and write
7
6
5
4
VC7
VC6
VC5
VC4
0
0
0
0
read and write
11
DE0
0
10
PD
0
9
8
MT
0
QM
0
3
2
1
0
VC3
0
VC2
0
VC1
0
VC0
0
Table 50:
DAC mixing channel 1, 3 and 5 registers (address 18h, 1Ah and 1Ch) bit
allocation
15
14
13
12
ICS1
ICS0
-
-
0
0
0
0
read and write
7
6
5
4
VC7
VC6
VC5
VC4
0
0
0
0
read and write
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
11
-
0
10
PD
0
9
8
MT
0
QM
0
3
2
1
0
VC3
0
VC2
0
VC1
0
VC0
0
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