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參數(shù)資料
| 型號： | UDA1384 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Multichannel audio coder-decoder |
| 中文描述： | 多聲道音頻編碼解碼器 |
| 文件頁數(shù)： | 19/55頁 |
| 文件大?。?/td> | 276K |
| 代理商： | UDA1384 |
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9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
19 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
10. I
2
C-bus interface
10.1 General
The UDA1384 has an I
2
C-bus microcontroller interface. All the features are accessible
with the I
2
C-bus interface protocol. In the I
2
C-bus mode, the DAC mute function is
accessible via pin MCMODE with signal QMUTE.
The exchange of data and control information between the microcontroller and the
UDA1384 is accomplished through a serial hardware interface comprising the following
pins as shown in
Table 11
:
MCCLK: clock line with signal SCL
MCDATA: data line with signal SDA
10.2 Characteristics of the I
2
C-bus
The bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to the supply voltage V
DD
via a pull-up resistor when connected to the output
stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus
from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a
pull-up resistor can be used, between 200 pF and 400 pF a current source or switched
resistor must be used). Data transfer can only be initiated when the bus is not busy.
10.3 Bit transfer
One data bit is transferred during each clock pulse (see
Figure 13
). The data on the SDA
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time will be interpreted as control signals. The maximum clock frequency is
400 kHz.
To be able to run on this high frequency, all the inputs and outputs connected to this bus
must be designed for this high-speed I
2
C-bus according to the Philips specification.
Table 15:
Byte
L3-bus read data
L3-bus
mode
Action
First in time
Bit 0
0
Latest in time
Bit 5
1
Bit 1
1
Bit 2
0
Bit 3
1
Bit 4
0
Bit 6
0
Bit 7
0
1
address
device
address
register
address
device
address
register
address
data
byte 1
data
byte 2
2
data
transfer
address
1
A6
A5
A4
A3
A2
A1
A0
3
1
1
0
1
0
1
0
0
4
data
transfer
data
transfer
data
transfer
0 or 1
A6
A5
A4
A3
A2
A1
A0
5
D15
D14
D13
D12
D11
D10
D9
D8
6
D7
D6
D5
D4
D3
D2
D1
D0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UDA1384H | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H/N1,518 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H/N1,557 | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1384H-T | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| UDA1431T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit, 48 kHz, low-cost stereo current DAC |
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