參數(shù)資料
型號： UDA1384
廠商： NXP Semiconductors N.V.
英文描述： Multichannel audio coder-decoder
中文描述： 多聲道音頻編碼解碼器
文件頁數(shù)： 29/55頁
文件大?。?/td> 276K
代理商： UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
29 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
11.4 Audio ADC and DAC subsystem settings
Table 28:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Audio ADC and DAC subsystem register (address 01h) bit allocation
15
14
13
12
DC
PAB
PAA
MTB
1
0
0
read and write
7
6
5
DAG
FIL
DVD
DIS1
0
0
0
read and write
11
MTA
0
10
AIF2
0
9
8
AIF1
0
AIF0
0
0
4
3
2
1
0
DIS0
0
DIF2
0
DIF1
0
DIF0
0
0
Table 29:
Bit
15
Description of the audio ADC and DAC subsystem register bit
Symbol
Description
DC
ADC DC-filter.
Bit DC enables the digital DC-filter of the ADC.
1 = DC-filtering is active (default)
0 = no DC-filtering
PAB
Polarity ADC 2 control.
Bit PAB controls the ADC 2 polarity.
1 = polarity is inverted
0 = polarity is not-inverted (default)
PAA
Polarity ADC 1 control.
Bit PAA controls the ADC 1 polarity.
1 = polarity is inverted
0 = polarity is not-inverted (default)
MTB
Mute ADC 2.
Bit MTB enables the digital mute of ADC 2.
1 = ADC 2 is soft muted
0 = ADC 2 is not muted (default)
MTA
Mute ADC 1.
Bit MTA enables the digital mute of ADC 1.
1 = ADC 1 is soft muted
0 = ADC 1 is not muted (default)
AIF[2:0]
ADC output data interface format.
A 3-bit value to select the used data
format to the I
2
S-bus ADC output interface. Default 000. See
Table 30
.
DAG
DAC gain switch.
Bit DAG selects the DAC gain.
1 = gain = 6 dB
0 = gain = 0 dB (default)
FIL
Filter selection.
Bit FIL selects the interpolation filter characteristics.
1 = slow roll-off
0 = sharp roll-off (default)
DVD
192 kHz sampling mode selection.
Bit DVD selects the oversampling rate
of the noise shaper.
1 = 64f
s
rate; used for 192 kHz and 176.4 kHz sampling frequencies
0 = 128f
s
rate (default)
DIS[1:0]
Data interface selection.
A 2-bit value to select the data interface
connection. Default 00. See
Table 31
.
DIF[2:0]
DAC input data interface format.
A 3-bit value to select the used data
format to the I
2
S-bus DAC input interface. Default 000. See
Table 30
.
14
13
12
11
10 to 8
7
6
5
4 to 3
2 to 0
相關(guān)PDF資料
PDF描述
UDA1384H Multichannel audio coder-decoder
UDN2878W-2 10A SCRS
UDZ2.4B Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode
UDZ10B Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode
UDZ12B Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UDA1384H 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
UDA1384H/N1,518 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
UDA1384H/N1,557 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LOW COST MULTICHANNEL CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
UDA1384H-T 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 LO CST MULTICH CODEC RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
UDA1431T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16-bit, 48 kHz, low-cost stereo current DAC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*