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參數(shù)資料
| 型號(hào)： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選） |
| 文件頁(yè)數(shù)： | 8/67頁(yè) |
| 文件大?。?/td> | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320C209 Pin Functions (Continued)
PIN
I/O/Z
DESCRIPTION
NAME
NO.
MEMORY CONTROL SIGNALS (CONTINUED)
WE
62
O/Z
Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15–D0).
Data can be latched by an external device on the rising edge of WE. WE is active on all external program,
data, and I/O writes. WE goes into the high-impedance state when OFF is active low.
RAM enable. RAMEN enables the 4K
×
16 words of on-chip RAM.
MULTIPROCESSING SIGNALS
Bus request signal. BR is asserted during access of external global data memory space. BR can be used
to extend the data memory address space by up to 32K words. BR goes into the high-impedance state
when OFF is active low.
RAMEN
37
I
BR
68
O/Z
BIO
9
I
Branch control input. BIO is polled by BIOZ instruction. If BIO is low, the TMS320C209 executes a
branch. If BIO is not used, it should be pulled high.
XF
75
O/Z
External flag output (latched software-programmable signal). XF is used for signaling other processors
in multiprocessing configurations or a general-purpose output pin.
IACK
79
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is
fetching the interrupt vector location designated by A15–A0. IACK also goes into the high-impedance
state when OFF is active low.
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
INT1
INT2
INT3
33
34
35
I
External-user interrupts. INT1–INT3 are prioritized and maskable by the interrupt-mask register and the
interrupt-mode bit. If INT1–INT3 are not used they should be pulled high.
NMI
36
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked via the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should
be pulled high.
RS
RS
4
6
I
Reset input. RS and RS cause the TMS320C209 to terminate execution and force the program counter
to 0. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS
affects various registers and status bits.
MP/MC
10
I
Microprocessor/microcontroller mode-select pin. If MP/MC is low, the on-chip ROM is mapped into
program space. When MP/MC is high, the device accesses off-chip memory.
OSCILLATOR/TIMER SIGNALS CLKIN1/2
CLKOUT1
77
O/Z
Master clock output signal. CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine
cycle is bounded by the rising edges of CLKOUT1. CLKOUT1 goes into the high-impedance state when
OFF is active low.
CLKMOD
74
I
Clock input mode. CLKMOD (when high) enables the clock doubler and phase lock loop on the clock
input signal. If the internal oscillator is not used, X1 should be left unconnected.
CLKIN/X2
X1
69
70
I
Clock input. The clock input to CLKIN/X2 operates at half of the internal machine rate if the phase lock
loop (PLL) is enabled (CLKMOD high), or twice the internal machine rate if the PLL is disabled. As X2,
the pin operates as the oscillator input with X1 being the oscillator output.
TOUT
72
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a
CLKOUT1 cycle wide.
PLL5V
38
I
PLL operating at 5 V. When PLL5V is operated at 5 V, PLL5V should be strapped high.
RES1
I = input, O = output, Z =high impedance
40
I
Reserved input pin. Do not connect to RES1.
A
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