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參數(shù)資料
| 型號： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關斷，先進的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關斷，先進的外圍，多種鎖相環(huán)可選） |
| 文件頁數(shù)： | 25/67頁 |
| 文件大小： | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 11. TMS320C209 Memory-Mapped Registers
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NAME
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external interface
ADDRESS
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DESCRIPTION
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IMR
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PRD
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DS@0004
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Interrupt mask register. IMR individually masks or enables the seven interrupts. The lower three bits align to the
three external interrupt pins (bit 0 ties to INT1, bit 1 to INT2, bit 2 to INT3). Bit 3 ties to the timer interrupt. Bits
4 and 5 are not used in the TMS320C209. Bit 6 is reserved for monitor mode emulation operations and should
always be set to 0 except in conjunction with emulation monitor operations. Bits 7–15 are not used in the
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IS@FFFD
down ratio to 0 and starts the timer.
Timer period register. PRD contains the 16-bit period that is loaded into the timer counter when the counter
borrows or when the reload bit is activated. Reset initializes the PRD to 0xFFFF.
reset.
maskable interrupts. The lower three bits align to the three external interrupt pins (bit 0 ties to INT1N, bit 1 to
INT2N, bit 2 to INT3N). Bit 4 ties to the timer interrupt. Bits 5 and 6 are not used in the TMS320C209. Bit 7 is
reserved for monitor mode emulation operations and should always be set to 0 except in conjunction with
emulation monitor operations. A 1 indicates an active interrupt in the respective interrupt location. Writing a 1
to the respective interrupt bit clears an active flag and the respective pending interrupt. Writing a 1 to an inactive
flag has no affect. IFR is set to 0 at reset.
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IFR
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DS@0006
Interrupt flag register. IFR indicates that the T320C2xLP core has latched an interrupt pulse from one of the
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TCR
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IS@FFFC
Timer control register. TCR contains the control bits that define the divide down ratio, start/stop the timer, and
reload the period. Also contained in TCR is the current count in the prescaler. Reset initializes the timer divide
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data, and I/O space as well as the address visibility enable bit. Reset initializes WSGR to 0xF.
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The TMS320C2xx can address up to 64K
×
16 words of memory or registers in each of the program, data, and
I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high 32K
words can be dynamically mapped either local or global using the GREG register as described in the
TMS320C2xx User’s Guide A data-memory access mapped as global asserts BR low (with timing similar to
the address bus) (see Table 8).
The CPU of the TMS320C2xx schedules a program fetch, data read, and data write on the same machine cycle.
This is because from on-chip memory the CPU can execute all three of these operations in the same cycle.
However, the external interface multiplexes the internal buses to one address and one data bus. The external
interface sequences these operations to complete first the data write, then the data read, and finally the program
read.
The ’C2xx supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, thus maximizing system throughput. The full 16-bit address and data bus,
along with the PS, DS, and IS space select signals, allow addressing of 64K 16-bit words in each of the three
spaces.
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
The ’C2xx external parallel interface provides various control signals to facilitate interfacing to the device. The
R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles. For convenience, the device also provides the RD and the
WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those
cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to
the ’C2xx.
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