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參數(shù)資料
| 型號： | TMS320VC203 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關斷，先進的外圍，多種PLL可選) |
| 中文描述： | 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關斷，先進的外圍，多種鎖相環(huán)可選） |
| 文件頁數(shù)： | 7/67頁 |
| 文件大?。?/td> | 1452K |
| 代理商： | TMS320VC203 |
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320C209 Pin Functions
PIN
I/O/Z
DESCRIPTION
NAME
NO.
ADDRESS AND DATA BUSES
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
11
13
14
16
17
18
19
20
23
24
25
26
27
28
30
31
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the
core CPU and external data/program memory or I/O devices. D15–D0 are placed in the
high-impedance state when not outputting or when RS is asserted. They also go into the high-impedance
state when OFF is active low. D15–D0 are also used in external DMA access of the on-chip
single-access RAM.
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
60
59
58
57
55
54
53
52
49
48
46
45
44
43
42
39
O/Z
Parallel address bus A15 (MSB) through A0 (LSB). A15–A0 are multiplexed to address external
data/program memory or I/O. A15–A0 go into the high-impedance state when OFF is active low.
A15–A0 are used as inputs for external DMA access of the on-chip single-access RAM.
MEMORY CONTROL SIGNALS
DS
63
O/Z
Data select signal. DS is always high unless low level asserted for communicating to off-chip program
space. DS goes into the high-impedance state when OFF is active low.
PS
65
O/Z
Program select signal. PS is always high unless low-level asserted for communicating to off-chip
program space. PS goes into the high-impedance state when OFF is active low.
IS
64
O/Z
I/O space select signal. IS is always high unless low level asserted for communicating to I/O ports. IS
goes into the high-impedance state when OFF is active low.
READY
7
I
Data-ready input. READY indicates that an external device is prepared for the bus transaction to be
completed. If READY is not (READY low), the TMS320C209 waits one cycle and checks READY again.
If READY is not used it should be pulled high.
R/W
66
O/Z
Read/write signal. R/W indicates transfer direction when communicating to an external device.
Normally in read mode (high), unless low-level is asserted for performing a write operation. R/W goes
into the high-impedance state when OFF is active low.
STRB
67
O/Z
Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes
into the high-impedance state when OFF is active low.
RD
78
O/Z
Read select. RD indicates an active, external read cycle and can connect directly to the output enable
(OE) of external devices. RD is active on all external program, data, and I/O reads. RD goes into the
high-impedance state when OFF is active low.
I = input, O = output, Z =high impedance
A
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| TMS320VC33PGE120G4 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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