參數(shù)資料
型號: TMS320VC203
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(50ns指令周期, 空閑狀態(tài)CPU全關(guān)斷,先進(jìn)的外圍,多種PLL可選)
中文描述: 數(shù)字信號處理器(50ns的指令周期,空閑狀態(tài)CPU的全關(guān)斷,先進(jìn)的外圍,多種鎖相環(huán)可選)
文件頁數(shù): 14/67頁
文件大?。?/td> 1452K
代理商: TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
architectural overview
The ’C2xx advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memory bus structures, program and data, for full-speed execution. This multiple bus allows both reading data
and instructions simultaneously. Instructions support data transfers between the two spaces. This architecture
permits coefficients stored in program memory to be read in RAM, eliminating the need for a separate coefficient
ROM. This, coupled with a four-deep pipeline, allows the TMS320C2xx to execute most instructions in a single
cycle.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from the ST0 and ST1 except the INTM bit which is not affected by the LST
instruction). The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 1 shows the organization of status registers ST0 and ST1, indicating all status bits contained
in each. Several bits in the status registers are reserved and read as logic 1s. Refer to Table 4 for status register
field definitions.
ARP
OV
OVM
1
INTM
DP
15–13
12
11
10
9
8
7
6
5
4
3
2
1 0
ARB
CNF
TC
SXM
C
15–13
12
11
10
9
1
8
1
7
1
6
1
5
XF
4
1
3
1
2
PM
1–0
ST0
ST1
Figure 1. Status and Control Register Organization
A
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