參數(shù)資料
型號: TMS320VC203
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(50ns指令周期, 空閑狀態(tài)CPU全關(guān)斷,先進的外圍,多種PLL可選)
中文描述: 數(shù)字信號處理器(50ns的指令周期,空閑狀態(tài)CPU的全關(guān)斷,先進的外圍,多種鎖相環(huán)可選)
文件頁數(shù): 32/67頁
文件大小: 1452K
代理商: TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There
are two types of immediate addressing: long and short. In short immediate addressing, the data is contained
in a portion of the bits in a single-word instruction. In long immediate addressing, the data is contained in the
second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need
to be stored or used more than once during the course of program execution, such as initialization values,
constants, etc.
The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference
to a specific register, or implicitly with instructions that intrinsically reference certain registers. In either case,
operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand
address or immediate value.
repeat feature
The repeat function can be used with instructions (as defined in Table 16) such as multiply/accumulates (MAC
and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW).
These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they
effectively become single-cycle instructions. For example, the table-read instruction may take three or more
cycles to execute, but when the instruction is repeated, a table location can be read every cycle.
The repeat counter (RPTC) is loaded with the addressed data memory location if direct or indirect addressing
is used, an 8-bit immediate value if short immediate addressing is used. The RPTC register is loaded by the
RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared by reset.
Once a repeat instruction (RPT) is decoded, all interrupts including NMI (except reset) are masked until the
completion of the repeat loop. However, the device responds to the HOLD signal while executing an RPT loop.
instruction set summary
This section summarizes the opcodes of the instruction set for the ’C2xx digital signal processors. This
instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged according to
function and are alphabetized by mnemonic within each category. The symbols in Table 8 are used in the
instruction set opcode table (Table 16). The Texas Instruments ’C2xx assembler accepts ’C2x instructions.
The number of words that an instruction occupies in program memory is specified in column 3 of Table 16.
Several instructions specify two values separated by a
slash mark
(/) for the number of words. In these cases,
different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies
one word when the operand is a short immediate value or two words if the operand is a long immediate value.
The number of cycles that an instruction requires to execute is in column 3 of Table 16. All instructions are
assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The
cycle timings are for single-instruction execution, not for repeat mode.
A
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