參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 28/67頁
文件大小： 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
software-controlled wait-state generator
Table 12. ’C209 Wait-State Generator Control Register (WSGR)
TERMINAL
NAME
DESCRIPTION
0
PSWS
External program-space wait state on. When active, PSWS = 1 applies one wait state to all reads to off-chip
program space (writes always take at least two cycles regardless of PSWS or READY). The memory cycle can
be further extended using the READY signal. However, the READY signal does not override the wait state
generated by PSWS. This bit is set to 1 (active) by reset (RS or RS).
1
DSWS
External data-space wait state on. When active, DSWS = 1 applies one wait state to all reads to off-chip data
space (writes always take at least two cycles regardless of DSWS or READY). The memory cycle can be further
extended using the READY signal. However, the READY signal does not override the wait state generated by
DSWS. This bit is set to 1 (active) by reset (RS or RS).
2
ISWS
External input-/output-space wait state on. When active, ISWS = 1 applies one wait state to all reads to off-chip
I/O space (write always takes at least two cycles regardless of ISWS or READY). The memory cycle can be fur-
ther extended using the READY signal. However, the READY signal does not override the wait state generated
by ISWS. This bit is set to 1 (active) by reset (RS or RS).
3
AVIS
Address visibility. When active high, AVIS presents the internal program address out of the logic-interface
address bus if the bus is not currently used in an external memory operation. The internal address is presented
to provide a trace mechanism of internal code operation. Therefore, the memory-control signals are not active.
AVIS is set to 1 (active) by reset (RS or RS). AVIS should be deactivated in production systems to reduce system
power and noise.
TMS320C203
The software wait-state generator can be programmed to generate between 0 and seven wait states for a given
space. The WSGR has 12 bits: three DATA, six PROGRAM, and three I/O. The wait state generator inserts a
wait state(s) to a given memory space based on the value of the three bits, regardless of the condition of the
READY signal. The READY signal can be used to extend wait state further. All bits are set to 1 at reset so that
the device can operate from slow memory from reset. The WSGR register (shown in Figure 5 and
Table 13 and Table 14) resides at I/O port 0xFFFF.
15–12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
ISWS
DSWS
PSUWS
PSLWS
0
W
W
W
W
Figure 5. TMS320C203 Wait-State Generator Control Register (WSGR)
Table 13. TMS320C203 Wait-State(s) Programming
BITS 11, 8, 5, 2
BITS 10, 7, 4, 1
BITS 9, 6, 3, 0
WAIT-STATES FOR PROGRAM, DATA, AND I/O
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
A
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