參數(shù)資料
型號： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁數(shù)： 45/67頁
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
LOW-POWER DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
400
μ
A (all outputs)
1.5 V
60-pF typical load-circuit capacitance
Figure 8. Test Load Circuit
signal-transition levels
The data in this section is shown for both the 5-V version (’C2xx) and the 3.0-V version (’VC2xx). In each case,
the 5-V data is shown followed by the 3-V data in parentheses. TTL-output levels are driven to a minimum
logic-high level of 2.4 V (2 V) and to a maximum logic-low level of 0.6 V (0.4 V). Figure 9 shows the TTL-level
outputs.
0.4 V
0.8 V
2 V
2.4 V
Figure 9. TTL-Level Outputs
TTL-output transition times are specified as follows:
For a high-to-low transition the level at which the output is said to be no longer high is 2 V (1.8 V) and the
level at which the output is said to be low is 1 V (0.8 V).
For a low-to-high transition the level at which the output is said to be no longer low is 1 V (0.8 V) and the
level at which the output is said to be high is 2 V (1.6 V).
Figure 10 shows the TTL-level inputs.
2 V (90%)
0.8 V (10%)
Figure 10. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
For a high-to-low transitionon an input signal, the level at which the input is said to be no longer high is
2 V (1.8 V) and the level at which the input is said to be low is 0.8 V (0.4 V).
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V (0.4 V) and the level at which the input is said to be high is 2 V (1.8 V).
A
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