參數(shù)資料
型號: TMS320AV220
廠商: Texas Instruments, Inc.
英文描述: Video CD MPEG Decoder(視頻CD MPEG編碼器)
中文描述: 視頻CD MPEG解碼器(視頻光盤的MPEG編碼器)
文件頁數(shù): 6/31頁
文件大?。?/td> 612K
代理商: TMS320AV220
TMS320AV220
VIDEO CD MPEG DECODER
SCSS016A – JUNE 1994 – REVISED JANUARY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
VCC
6, 16, 27,
37, 42, 50,
58, 68, 77,
82, 91,
101, 113,
122, 123,
129, 141,
152, 159
5-V supply voltage
VCLK
137
I
Video clock. The ’AV220 outputs one pixel on PD23–PD0 for each cycle of VCLK. VCLK can not run
faster than one-half the frequency of SYSCLK and is typically 13.5 MHz. VCLK ties directly to the
CLK135 output of the TMS320AV420 NTSC encoder.
VOE
143
I
Video output enable, active low. VOE must be low for the ’AV220 to drive the pixel data bus
(PD23–PD0). When VOE is high, the pixel data bus is in a high-impedance state.
VSYNC
124
I
Vertical synchronization. VSYNC controls the ’AV220 pixel-data output frame timing. VSYNC ties
directly to the VSYNC output of the TMS320AV420 .
WAIT
85
O
Wait request to host, active low. WAIT low requests the host to wait during register read and write
cycles. If an access is attempted during the reset period, the chip activates the WAIT line until the reset
is completed. WAIT is an open-drain output.
WE
15
O
Write enable, active low. When low, WE requests a write to the DRAM and reads from the DRAM when
high.
WR
90
I
Write strobe, active low. WR is used by the host when writing to ’AV220 registers.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320AV220PCM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG
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