參數(shù)資料
型號(hào)： TMS320AV220
廠商： Texas Instruments, Inc.
英文描述： Video CD MPEG Decoder(視頻CD MPEG編碼器)
中文描述： 視頻CD MPEG解碼器（視頻光盤的MPEG編碼器）
文件頁(yè)數(shù)： 11/31頁(yè)
文件大?。?/td> 612K
代理商： TMS320AV220
TMS320AV220
VIDEO CD MPEG DECODER
SCSS016A – JUNE 1994 – REVISED JANUARY 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DMA_MODE, DMA control (242Ch)
This register allows pseudo-DMA control of the ’AV220. Pseudo DMA is DMA transfers with flow control via
’AV220 interrupts and registers. The DMA_MODE register’s primary use is with the ’AV220 SANYO transfer
mode. The ’AV220 SONY mode is an on-demand mode and does not necessitate the use of this register. The
DMA_MODE register is defined as follows:
BIT NO.
FUNCTION
DEFAULT
VALUE
4
DMA-mode enable. When set pseudo-DMA control is enabled.
0
3:1
DMA-block size. Sets the amount of free space checked within the ’AV220 audio buffer. Sizes available
are:
000 : no selction
001 : 0.5 Kbytes
010 : 1 Kbytes
011 : 1.5 Kbytes
100 : 2 Kbytes
101 : 2.5 Kbytes
110 : 3 Kbytes
111 : 3.5 Kbytes
000
0
DMA done. Set by the host when the current DMA operation is complete.
0
To operate in the pseudo-DMA mode, the DMA request interrupt must be enabled (bit 7 of INTR_EN), the DMA
mode must be enabled (bit 4 of DMA_MODE), and the desired DMA-block size is selected (bits 3:1 of
DMA_MODE). When the ’AV220 wants MPEG data a DMA_request (interrupt) is generated. When the host
services the ’AV220 interrupt, it inquires on the ’AV220 video-buffer fullness using the steps listed below. After
calculating the amount of room left in the buffer, the host determines if room is available for the desired DMA
block size. If so, then a new block of MPEG data can be transferred using a host DMA mechanism. These DMA
blocks can be transferred at the maximum transfer rate; that is, CDREAD occurs immediately after CDEN
assertion.
To inquire on the video-buffer fullness, the following two writes must be performed. Two bytes are then read,
which is the buffer fullness.
ADDRESS DATA
1.
2088
w
0B
2.
2089
w
00
3.
208C
r
low byte
4.
208D
r
high byte
DRAM_SEL, DRAM page select, 5:0 (2428h)
DRAM_SEL selects one of 64 8-K DRAM pages and acts as the six most significant bits of the DRAM address
for reads or writes. This register allows full random access to the DRAM. DRAM access takes multiple clock
cycles.
FAST, fast-forward/fast-reverse mode (2421h)
0 = Normal operation
1 = Fast-forward/fast-reverse mode. The bit-stream buffer is flushed, PTS checking is disabled, only
I-frames are displayed, and audio is muted.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320AV220PCM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG
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